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Topic: large data stream minimal latency (Read 471 times) previous topic - next topic


I'm looking at the Due for the A/D 1Msps for a project
roughly 2k data /ms - continous for 20-100sec  (200Meg ? or so ..)
if read about fat testing with SD for nearing 5M/s writing to flash which theorticaly should be fast enough
but since the data continously the latency could overwhelm the system  ....

(what i'd really like is a 1gig ram fifo & write at my leasure ... )

I've done asm language so not tooo scarry but ... feasible ??


This is exactly why the Arduino team should have allowed access to the external memory interface on the Due. Unfortunately they didn't.

There has been some threads here about ADC sampling speeds and the porting of sdfat to the Due that may help.


I can't find the ADC thread but it's here somewhere.

Rob Gray aka the GRAYnomad www.robgray.com


ya / read most of those / very disapointed about the mem interface (WTF!!??)  sigh ..
Had not seen the bits about the DMA though .. looks very promising

consided making a multi chip spi ram board (16x 64Mbit =128MBytes ) 
   but that doen't fit in my time line ( & i don't have my tools, due to other complex reasons ..)

or i skip the due & look at a AVR board ...


or i skip the due & look at a AVR board ...

Which AVR, not many have external memory interfaces and they will be slower than the ARM.

Rob Gray aka the GRAYnomad www.robgray.com

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