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Topic: SPI without SS is not possible? (Read 1 time) previous topic - next topic

acid

// SCK, MOSI and SS as outputs
DDRB |= (1<<2)|(1<<3)|(1<<5);

SPCR |= (1<<MSTR); // Set as Master
SPCR |= (1<<SPR0)|(1<<SPR1); // divided clock by 128
SPCR |= (1<<SPE); // Enable SPI

After this configuration on ATMega328, I'm able to send data. However, I don't need SS pin, in fact I'm using SS pin as GPIO and if I configure ONLY SCK and MOSI, data is not going out. Is there any way to make SPI work without SS pin? I'm simply connecting Master SPI to USI in two wire mode, totally no need in SS.

CrossRoads

SS must be set as output pin on the master and an input pin on the slave per the Atmel datasheet.
The master may then use another pin as the SS out to the slave, or not, but SS must be an output.
If SS is not set as output, it must remain high on the master device:

19.3 SS Pin Functionality
19.3.1 Slave Mode
When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is
activated, and MISO becomes an output if configured so by the user. All other pins are inputs. When SS is driven
high, all pins are inputs, and the SPI is passive, which means that it will not receive incoming data. Note that the
SPI logic will be reset once the SS pin is driven high.
The SS pin is useful for packet/byte synchronization to keep the slave bit counter synchronous with the master
clock generator. When the SS pin is driven high, the SPI slave will immediately reset the send and receive logic,
and drop any partially received data in the Shift Register.
19.3.2 Master Mode
When the SPI is configured as a Master (MSTR in SPCR is set), the user can determine the direction of the SS pin.
If SS is configured as an output, the pin is a general output pin which does not affect the SPI system. Typically, the
pin will be driving the SS pin of the SPI Slave.
If SS is configured as an input, it must be held high to ensure Master SPI operation. If the SS pin is driven low by
peripheral circuitry when the SPI is configured as a Master with the SS pin defined as an input, the SPI system
interprets this as another master selecting the SPI as a slave and starting to send data to it. To avoid bus contention,
the SPI system takes the following actions:
1. The MSTR bit in SPCR is cleared and the SPI system becomes a Slave. As a result of the SPI becoming a
Slave, the MOSI and SCK pins become inputs.
2. The SPIF Flag in SPSR is set, and if the SPI interrupt is enabled, and the I-bit in SREG is set, the interrupt
routine will be executed.
Thus, when interrupt-driven SPI transmission is used in Master mode, and there exists a possibility that SS is
driven low, the interrupt should always check that the MSTR bit is still set. If the MSTR bit has been cleared by a
slave select, it must be set by the user to re-enable SPI Master mode.

Designing & building electrical circuits for over 25 years. Check out the ATMega1284P based Bobuino and other '328P & '1284P creations & offerings at  www.crossroadsfencing.com/BobuinoRev17.
Arduino for Teens available at Amazon.com.

acid

Thanks,

In SPI Master mode I can't use MISO pin as GPIO pin? Seems there is nothing about it in documentation. Basically I am using only MOSI and SCK pins.

CrossRoads

MISO is committed for SPI operation, expecting data back from slave.  Read more in 19.0
Designing & building electrical circuits for over 25 years. Check out the ATMega1284P based Bobuino and other '328P & '1284P creations & offerings at  www.crossroadsfencing.com/BobuinoRev17.
Arduino for Teens available at Amazon.com.

acid

Then I guess will have to use SPI bit banging.

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