I'm using the 2560 in my board design - so have plenty of pins to interface with the chip.
That's not an option if you want to use the "External Address Interface" of the AVR (which puts the external memory actually IN the address space so that you don't need special subroutines to access it.) The AVR external interface is always "multiplexed" to save some pins (it probably originated on a 40pin chip.)
it seems that the latch holds half the address, while the other half is provided by the other 8 address pins of the MCU
whilst the data bits are then provided by the latches inputs?
The data bits of the RAM are then connected to the AD0-7 pins of the AVR. Once the address is latched from the previous clock cycle, the fact that the input to the latch is also connected to those pins is irrelevant.
You won't get "zero wait" RAM (external RAM is slower than internal RAM), but it should be faster than any other way of doing things.
The sequence looks like:
Provide A0-A15 on AD0-7 and A8-15.
Enable the Latch (ALE). A0-A7 are now sent to the memory by the latch outputs, and A8-A15 by the AVR (still)
Either set AD0-7 to the data and signal "WR" for a write to RAM, or signal "RD" and read AD0-7 as inputs to the AVR.