QuoteI'm using the 2560 in my board design - so have plenty of pins to interface with the chip.That's not an option if you want to use the "External Address Interface" of the AVR (which puts the external memory actually IN the address space so that you don't need special subroutines to access it.) The AVR external interface is always "multiplexed" to save some pins (it probably originated on a 40pin chip.)You won't get "zero wait" RAM (external RAM is slower than internal RAM), but it should be faster than any other way of doing things.
I'm using the 2560 in my board design - so have plenty of pins to interface with the chip.
Or do you mean it's simply not zero wait due to the fact the address has to be latched?
That's not an option? Sorry, I don't follow
The datasheet says "Accessing external SRAM takes one additional clock cycle per byte compared to access of the internal SRAM." (not including any wait-states that are configured.) It's not entirely obvious whether that's because of the multiplexing, or for some other reason.
that would say to me that's the latch signal as that is the only additional step it is taking as compared to internal SRAM is it not?