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Topic: ...a hand explaining this RAM shield please? (Read 839 times) previous topic - next topic

jtw11


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I'm using the 2560 in my board design - so have plenty of pins to interface with the chip.

That's not an option if you want to use the "External Address Interface" of the AVR (which puts the external memory actually IN the address space so that you don't need special subroutines to access it.)  The AVR external interface is always "multiplexed" to save some pins (it probably originated on a 40pin chip.)

You won't get "zero wait" RAM (external RAM is slower than internal RAM), but it should be faster than any other way of doing things.


That's not an option? Sorry, I don't follow - the 2560 supports external memory in the manner you've described.

The first 56k of external RAM however is zero wait is it not, as the external memory map leaves a 56k 'slot' directly accessible without bank selection of the RAM chip?

Or do you mean it's simply not zero wait due to the fact the address has to be latched?

Your written sequence was especially useful, many thanks.

westfw

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Or do you mean it's simply not zero wait due to the fact the address has to be latched?

The datasheet says "Accessing external SRAM takes one additional clock cycle per byte compared to access of the internal SRAM." (not including any wait-states that are configured.)   It's not entirely obvious whether that's because of the multiplexing, or for some other reason.

I should add for the sake of more casual readers that the "sequence" is all done for you by the AVR internals.  You could imagine a very similar sequence done explicitly by the user program - output address to a couple of IO ports, fiddle with the memory signals using digitalWrite, read or write the data from another port, etc.  But you don't have to do that; that's what the "external memory interface" of the chip does.  (Similar to the way you COULD run SPI by doing "bit-banging", but the SPI peripheral does a lot of work for you.)

Graynomad

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That's not an option? Sorry, I don't follow

What Westfw is saying is that if you are using an Arduino none of the non-Mega versions are an option, the Mega is the only one with the external memory interface.

The schematic looks correct, except that AD8:15 are only addresses so probably should be called A8:15.

_____
Rob
Rob Gray aka the GRAYnomad www.robgray.com

jtw11

#8
Dec 18, 2012, 10:55 am Last Edit: Dec 18, 2012, 10:59 am by jtw11 Reason: 1
Brilliant, thanks - I'm with you both on all accounts. I'm not actually using the Arduino IDE for this project, so it's just co incidence that I'm using the 2560 chip in the design - I had looked at using a number of the smaller chips that supported external memory, but by the time I'd added external ADCs and port expanders / multiplexers to get my required I/O, a much bigger chip was cheaper and simpler.

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The datasheet says "Accessing external SRAM takes one additional clock cycle per byte compared to access of the internal SRAM." (not including any wait-states that are configured.)   It's not entirely obvious whether that's because of the multiplexing, or for some other reason.


If its one cycle per byte, and not per bit - that would say to me that's the latch signal as that is the only additional step it is taking as compared to internal SRAM is it not?

Graynomad

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that would say to me that's the latch signal as that is the only additional step it is taking as compared to internal SRAM is it not?
I would assume so, but it's of academic interest only I suppose.

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Rob
Rob Gray aka the GRAYnomad www.robgray.com

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