And what would you consider as "close" to the chip? Is 1in of wire/copper still "close"?
As close as possible means "as close as possible". And with wide (low-inductance) traces. Really fast ICs
(100MHz + clocking) need decoupling within 1 to 2 mm of each and every supply pin and a groundplane
is essential... These chips switch in fractions of a nanosecond and every tiny scrap of stray inductance
Somewhat slower logic like the Arduino I'd say 5mm--10mm is worth aiming for and ground plane or grid is really
desirable. Unless you have the test equipment to measure the true nano-second timescale dips on the
supply and ground caused by switching transients you cannot tell how much slack you have, so you decouple
conservatively to avoid nasty surprises.
The basic rule is the faster the logic the _smaller_ the decoupling capacitor is needed, but it must
be closer to the actual silicon (and usually more than one). The more current is switched the larger
the decoupling capacitor should be (or it should be split into a range of values with the smaller valued
ones closer to the chip).
Its hard to know the actual switched currents though, mostly these currents charge capacitances of
other MOSFETs on the chip and last for a few ns. You can get an estimate by looking at the current
consumption of a chip at its highest rated clockspeed - but that doesn't mean you need less decouplnig
if clocking at lower rates, since the switching transients are equally fast however seldom they happen.