Thanks for all the input so far, here are some screenshots of my layout - well, part placement at least.
So, the d-pak packages on the left hand side are power switching FETs / IGBTs. The gate drivers are the small ICs between the rows. The IGBTs subject to a large inductive spike are the top row, top and bottom layers. The h - bridge is the through hole 11 pin vertical package.
My power supply, i.e. regulator, fuses, tranzorb, caps etc is the is central where the two horizontal d-paks are. Underneath however is a general purpose low side driver chip to configure which external relays should be powered. These will only switch during power up / off really.
I wanted to move the power supply away from the IGBTs a little, but the ICs to the right of my power supply are conditioning ~10kHz AC signals, converting USB to UART, reading thermocouples etc.
Bottom right is a flash IC, latch & external RAM - I've tried to keep these as far away as possible as random memory corruptions are not something I'm keen on getting. The two ICs underneath the MCU are SPI devices, so I'm hoping there's not an issue there with noise? The jumpers are to select between external filters for these two ICs, and i've left room around there to route signals over to the left hand side gate drivers.
I've still got ~40 resistors, ~20 caps to pull on to the board from outside of the outline, but these are small 0603 parts, as are the ones present currently on the board.
Does anybody have any recommendations, comments, criticisms (constructive of course, this is the first PCB i've laid out, and my first venture into SMD - all my other projects have just been through hole on vero board)?
I would use as much free area top & bottom for ground polygon as you can.
Earlier on in the thread however, I was told I should avoid doing this as it will help interference get in to the ground. Or would that only typically be the case if I had a power component on the other side of the board, and I put a ground plane on the other?
Top and bottom, together -