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Topic: Signal inverter (Read 1 time) previous topic - next topic

GoingForGold

Hi!

I'm designing a inverter circuit, which is only applied on a "enable" signal, so no high speed needed.

My first thought was make it easy as this:



But in the WWW I found most designs to be like this:



I don't really understand for what this first resistor is needed. Could someone explain me this? Would my solution work?

Thanks!

retrolefty

No the first simpler one is perfectly OK. However that first one fails to include the required series current limiting base resistor between the output pin and the base terminal of the transistor. Damage to the driving signal and or the transistor is highly probable without it.

Lefty

Papa G

Quote
I don't really understand for what this first resistor is needed. Could someone explain me this? Would my solution work?


I think you mean "transistor" instead of "resistor". The answer to that question is that the second circuit can switch faster due to the potentially lower value of the base resistor, since the capacitance of the transistor junction would be able to charge and discharge faster. In practice, retrolefty's advice will no doubt work perfectly for your application. The second circuit is the classic input stage to a TTL integrated circuit and makes sense when you are building ICs because transistors and diodes take up less space on the die than resistors.

Docedison

#3
Feb 03, 2013, 05:22 pm Last Edit: Feb 04, 2013, 09:08 am by Docedison Reason: 1
No I don't think so... There is no base bias on the second transistor (it should be a PNP) the first transistor is cut off when the emitter is high when it's low there is nothing at the  collector for it to work with. This is a conceptually bad adaptation of a TTL gate input.
For a thought problem set that circuit up in your mind and ground the first transistor emitter...
Q: What happens?.
A: Since the base has a pull-up on it, it starts conducting...
Conducting What? there is no forward bias supply for the second transistor base, so nothing happens.


Bob
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Papa G


No I don't think so... There is no base bias on the second transistor (it should be a PNP) the first transistor is cut off when the emitter is high when it's low there is nothing at the  collector for it to work with. This is a conceptually bad adaptation of a ttl gate input.

Bob


Using the nomenclature from OP's circuit diagram: When the emitter of T2 is > 1.4V, T1 is biased into saturation through the 4k7 resistor and the forward biased PN junction of T2. When the emitter of T2 is low, T2 is saturated and its collector is lower than required to turn on T1 and the output is pulled up to 5V.

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