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Topic: SPI Mode (Read 423 times) previous topic - next topic

Krupski

Feb 06, 2013, 07:24 pm Last Edit: Feb 06, 2013, 07:29 pm by Krupski Reason: 1
Hi all,

I have been looking at this diagram for several days and for some reason I feel like I'm missing something.

What confuses me is that it says "Data is outputted [sic} on the falling edge of SCK" but it looks like data is output on the RISING edge!

Based on this diagram, I think this is SPI Mode 3. Am I right?

(by the way, CS1 and CS2 are just chip select pins for each "chip". The device has two "chips" (display drivers) sharing a common SPI bus).

Thanks.....

-- Roger
Gentlemen may prefer Blondes, but Real Men prefer Redheads!

Riva

I also think it's SPI mode 3

Krupski

#2
Feb 06, 2013, 08:49 pm Last Edit: Feb 07, 2013, 12:15 am by Krupski Reason: 1
Edit: Nevermind. I found my problem. I forgot to use a tilde for bit clearing!

I did this:

[font=monospace]Set bit: PORT != _BV(PIN); // right[/font]
[font=monospace]Clr bit: PORT &= _BV(PIN); // wrong![/font]

should have been

[font=monospace]Clr bit: PORT &= ~_BV(PIN); // wrong![/font]

Oh well......
Gentlemen may prefer Blondes, but Real Men prefer Redheads!

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