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Krupski
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« on: February 06, 2013, 01:24:58 pm »
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Hi all,

I have been looking at this diagram for several days and for some reason I feel like I'm missing something.

What confuses me is that it says "Data is outputted [sic} on the falling edge of SCK" but it looks like data is output on the RISING edge!

Based on this diagram, I think this is SPI Mode 3. Am I right?

(by the way, CS1 and CS2 are just chip select pins for each "chip". The device has two "chips" (display drivers) sharing a common SPI bus).

Thanks.....

-- Roger
« Last Edit: February 06, 2013, 01:29:29 pm by Krupski » Logged

Riva
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« Reply #1 on: February 06, 2013, 01:40:02 pm »
 Bigger Bigger Smaller Smaller Reset Reset
I also think it's SPI mode 3
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Krupski
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« Reply #2 on: February 06, 2013, 02:49:22 pm »
 Bigger Bigger Smaller Smaller Reset Reset
Edit: Nevermind. I found my problem. I forgot to use a tilde for bit clearing!

I did this:

Set bit: PORT != _BV(PIN); // right
Clr bit: PORT &= _BV(PIN); // wrong!

should have been

Clr bit: PORT &= ~_BV(PIN); // wrong!

Oh well......
« Last Edit: February 06, 2013, 06:15:09 pm by Krupski » Logged

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