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Topic: I/O loading on Due (Read 2089 times) previous topic - next topic


Any links to an answer appreciated

In Atmel PDF doc11057 (Sam3X reference) page 1391 (Para 46.2 DC characteristics) , is Rpulldown part of the internal circuitry, and does it only refer to TST, ERASE and JTAGSEL select pins ?
If so, is there a reference to the internal pulldown resistance for the general purpose I/O pins ?

Thanks in advance.


There are internall pull-up resistors for all the io pin, you can enable them with
Code: [Select]


Ok, I just located that in the Atmel doc too. However, I'd like to find out the approx value of the internal loading when pullup is disabled and whether that relates to the datasheet values.


Feb 14, 2013, 09:32 am Last Edit: Feb 14, 2013, 11:25 am by gbduino Reason: 1
What you might have overseen: On the same page of the data sheet you mentioned, the currents for the GPIO inputs with non activated resistors for pull-up/down are specified as Leakage current in the range of 2 to 30nA. This should answer your question for the load.
In case of activated resistors - for the Due I expect only the pullup mode to be implemented, although the specification for the Arm obviously also allows a pulldown mode >edit: - pulldown only for TST,ERASE and JTAGSEL<.


does it only refer to TST, ERASE and JTAGSEL select pins ?

In reference to the Atmel paper I would say so only on this pins

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