The P-Ch mostfet gate controlled with a neg voltage. if the source is at 12Volt, the gate can easely be pulled to a lower voltage and thereby creating a negative voltage.
Right - that explains it perfectly. I wondered why the BJT was there!
Without the BJT, and even with a 5V logic high, Vgs would still be effectively 5v-12v = -7V, and the FET would be on - take the gate to 12V, then 12v-12v = 0V and the FET is off.
EDIT - Saying that, this is all irrelevant to me, I'm driving the FET from the output of an op amp acting as a comparator, so I can simply have the power supply to the op amp the same as the source voltage of the P FETs, that way - when the comparator output is high, Vgs = 0v, when the output is low, Vgs = -Vsource