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Topic: ShiftPWM SPI Clock signal noise (Read 1 time) previous topic - next topic

azi

Hello,
I am using arduino mega 1280 with shiftpwm library to run couple of shiftregisters with uln2003 that drives high power leds. I had some noise problems with >2 registers connected. I suspected the CLK signal so I disconnected all the registers and plugged usbee logic analyzer straight into the clock pin. The latch and data signal looks good (probably because it's lower frequency), but the clock signal has lots of saw spikes here is image of it http://masz.in/spi_shift/clock%20signal.jpg
The clock is running @ 4Mhz. I guess that the longer cable the worst signal this is probably why the more registers i add the bigger noise i have. Do you have any idea how to resolve this issue? Schmitt Trigger? Low Pass/High Pass filtering? Help!

pylon

On this picture Digital 0 is the clock signal and Bus is the data signal? What's the sample rate of your USBee? More than 10MS/s? Doesn't look that bad to me. From the speed I'd guess you're using the hardware SPI, aren't you?

Can you define "noise problems"? How do these show up?

CrossRoads

Do you have decoupling caps on the shift register Vcc pins (0.1uF cap from +5 to Gnd near the Vcc  pin)?

You could also look at terminating the clock line to clean it up.
http://www.fairchildsemi.com/an/AN/AN-393.pdf
Designing & building electrical circuits for over 25 years.  Screw Shield for Mega/Due/Uno,  Bobuino with ATMega1284P, & other '328P & '1284P creations & offerings at  my website.

azi


On this picture Digital 0 is the clock signal and Bus is the data signal? What's the sample rate of your USBee? More than 10MS/s? Doesn't look that bad to me. From the speed I'd guess you're using the hardware SPI, aren't you?

Can you define "noise problems"? How do these show up?


Both signals are clock, one is "analog" reading the other is digital. Usbee runs at 16mbps.

http://m.youtube.com/#/watch?v=SR9LhPwdWqg this is how it looks like. There should be one triangle lit up at one time.

And yes its hardware SPI that ShiftPWM uses on Mega its 52,51 and 8 for latch

azi


Do you have decoupling caps on the shift register Vcc pins (0.1uF cap from +5 to Gnd near the Vcc  pin)?

You could also look at terminating the clock line to clean it up.
http://www.fairchildsemi.com/an/AN/AN-393.pdf


Yes I do have decoupling, on power line 100nF, 1uF, 10uF. Also on the 595 chips between vcc and gnd 100nF just on top of the register.
By terminating you mean for ex. from last clock 10k resistor to gnd?

pylon

16Ms/s is not enough to get a realistic picture of a 4MHz clock signal.

The lower part of the picture is very strange because the digital interpretation and the analog signal curve doesn't look synchronized. Is this offset normal for the USBee or are these different signals?

CrossRoads

"By terminating you mean for ex. from last clock 10k resistor to gnd?"
Yes, or look at some of the examples in the article
Your image capture might also look worse than it really is, can be impacted by things like where your probe grounds were connected.
Designing & building electrical circuits for over 25 years.  Screw Shield for Mega/Due/Uno,  Bobuino with ATMega1284P, & other '328P & '1284P creations & offerings at  my website.

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