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Topic: Inrush current protection using MOSFETs (Read 1 time) previous topic - next topic

Erdin

Sorry, I was thinking about schematics like this: http://circuit-zone.com/index.php?electronic_project=438

About figure 1 on page 8:
If Vgg is pulled low (to switch on the mosfet) the Gate voltage is lowered.
The lowering of the Gate voltage is already slowed down by Cgd.
The rising voltage on Vout pushes current through Cgd and Rgd.
That current raises the Gate voltage and is working against Vgg. So it is preventing a fast voltage ramp of Vout.

Figure 2 on page 8 is confusing.
Vgs is negative, so more negative indicates that the Vgs is getting bigger.
If the curve of Vgs is lowered, the mosfet is switched on more.

jtw11

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Sorry, I was thinking about schematics like this: http://circuit-zone.com/index.php?electronic_project=438


No worries, I thought something was up....

Perhaps I've misinterpreted the app note entirely, so let's start from basics.

VGG is not a connection from another device such as an NPN transistor, but it's simply the power supply ground? Your wording seems to imply VGG is controlled by another device not pictured.

Figure 3 that uses an N MOSFET on the high side, I think I understand - as of course - when the circuit is powered up, VDD = 12V (for arguments sake) and so the gate is charged through CGD' and RGD, slowly - which prevents inrush.

Is that correct? Further, I didn't think you should/could ever use NMOS on the high side?

Only when we've sorted these issues, then let's move onto the PMOS application of Figure 1  :)

Cheers!

Erdin

#7
Mar 19, 2013, 09:10 pm Last Edit: Mar 19, 2013, 09:11 pm by Erdin Reason: 1
Well, if we have so much trouble with the document, the document is not written very well.

Using N-channel on high side would be possible if a voltage for the gate is available that is higher than the source or the drain. Like I wrote, that is almost never the case.

I see your point.
Page 8, figure 1.
Suppose Vgg is a low voltage or even ground.
If Vdd is switched on, the voltage on both sides of the capacitor is low, so the mosfet turns on.
But the fast rising of Vout causes a current through the capacitor towards the gate. The voltage on both sides of the capacitor is still the same, until the capacitor is slowly charged. That works agains the gate voltage, causing a slower rise of Vout.

I don't know what else I can make of it. I don't have the time to build a few circuits (that would be the way for me to understand it). Perhaps someone else can shine some light on this.

jtw11

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Using N-channel on high side would be possible if a voltage for the gate is available that is higher than the source or the drain. Like I wrote, that is almost never the case.


That I don't have, so that removes that possibility.

As for the PMOS application, yes - let's hope some others can chime in here too...

Cheers!

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