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Author Topic: Inrush current protection using MOSFETs  (Read 1578 times)
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Hi all,

So - to prolong the life of all the caps on a design I'm working on, and to prevent tripping of anything, I've been looking at inrush protection using MOSFETs. Now, Motorola have a nice app note, AN1542 about this exact issue. http://www.bonavolta.ch/hobby/files/MotorolaAN1542.pdf

However, there's a couple of little caveats that I don't quite understand.

Figure 3 on page 8 uses an NMOS FET to control inrush current by charging the gate slowly, i.e. limiting how fast gate voltage rises. Of course, with N FETs, VGS must be positive for the device to turn on. So the schematic makes sense.

However, a question - I thought one should never use NMOS in a high side application, only ever in the ground return?

Figure 1 however, also on page 8, uses PMOS to do the same job. However - I can't figure it out, P FETs require VGS to be negative for the device to turn on. So, question - when you first apply power to the circuit, the source is say 12V, and the gate is at 0V, so VGS is negative - and the FET is switched fully on, defeating the point entirely?

Am I wrong?
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Could you explain "defeating the point entirely", even Google translate can't help me.

You can use N-channel MOSFET at the high side, as long as you are able to make the Gate voltage high enough (higher than the Drain and Source). That is almost never the case, so it is not often used.

In Figure 1, the 12V is the Source pin of the P-channel MOSFET.
If the Gate is low, the P-channel MOSFET is switched on.
If the Drain is 12V, the Load is powered. But the Gate is still low and the Source is still 12V, keeping it switched on.
To slowly switch the load on, the Gate voltage has to be lowered slowly from 12V to a lower voltage.
Does that answer your question ?
« Last Edit: March 19, 2013, 09:20:14 am by Erdin » Logged

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Thanks for your reply.

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In Figure 1, the 12V is the Source pin of the P-channel MOSFET.
If the Gate is low, the P-channel MOSFET is switched on.
If the Drain is 12V, the Load is powered. But the Gate is still low and the Source is still 12V, keeping it switched on.
To slowly switch the load on, the Gate voltage has to be lowered slowly from 12V to a lower voltage.
Does that answer your question ?

I'm afraid not, no - the whole purpose of the solutions proposed in the app note are to ramp the MOSFETs on slowly so as to prevent high inrush currents.

If as you say, the gate is at 0 volts (because it's connected to the 0v rail), and you apply power to the circuit, i.e the source becomes 12V - then VGS is -12V, and the MOSFET is switched fully on, which then allows a large inrush current to flow immediately.

Hence, defeats the point entirely.
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We do have a misunderstanding, and I still don't know what "defeats the point entirely" means.

We are talking about figure 1, right ?
With the P-channel MOSFET on the high side.

Normally, when everything is off, the Gate should be the same as the Source. For example with a resistor from Gate to Source to keep the Gate at 12V.
If the Load is switched on slowly, the Gate should be slowly lowered from 12V to a lower voltage. Perhaps with a NPN-transistor with its collector to the Gate.

I can't tell it more clear than this.
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When I say defeats the point entirely, I am referring to the fact that the circuits presented are there to switch the load on slowly, whilst Figure 1 does not seem to do this.

So yes, we're talking about Figure 1, for sure.

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For example with a resistor from Gate to Source to keep the Gate at 12V.
If the Load is switched on slowly, the Gate should be slowly lowered from 12V to a lower voltage. Perhaps with a NPN-transistor with its collector to the Gate.

Figure 1 does not have a gate-source resistor, nor any NPN transistor for this purpose.

RGD and CGD' are there to provide the slow ramp of gate voltage - like I said in my original post, I understand how these passives are doing exactly that in Figure 3, but not in Figure 1. As Figure 1 defaults to on, i.e. does not prevent inrush current, hence - defeats the point, as the point is to prevent inrush current.
« Last Edit: March 19, 2013, 01:56:54 pm by jtw11 » Logged

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Sorry, I was thinking about schematics like this: http://circuit-zone.com/index.php?electronic_project=438

About figure 1 on page 8:
If Vgg is pulled low (to switch on the mosfet) the Gate voltage is lowered.
The lowering of the Gate voltage is already slowed down by Cgd.
The rising voltage on Vout pushes current through Cgd and Rgd.
That current raises the Gate voltage and is working against Vgg. So it is preventing a fast voltage ramp of Vout.

Figure 2 on page 8 is confusing.
Vgs is negative, so more negative indicates that the Vgs is getting bigger.
If the curve of Vgs is lowered, the mosfet is switched on more.
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Sorry, I was thinking about schematics like this: http://circuit-zone.com/index.php?electronic_project=438

No worries, I thought something was up....

Perhaps I've misinterpreted the app note entirely, so let's start from basics.

VGG is not a connection from another device such as an NPN transistor, but it's simply the power supply ground? Your wording seems to imply VGG is controlled by another device not pictured.

Figure 3 that uses an N MOSFET on the high side, I think I understand - as of course - when the circuit is powered up, VDD = 12V (for arguments sake) and so the gate is charged through CGD' and RGD, slowly - which prevents inrush.

Is that correct? Further, I didn't think you should/could ever use NMOS on the high side?

Only when we've sorted these issues, then let's move onto the PMOS application of Figure 1  smiley

Cheers!
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Well, if we have so much trouble with the document, the document is not written very well.

Using N-channel on high side would be possible if a voltage for the gate is available that is higher than the source or the drain. Like I wrote, that is almost never the case.

I see your point.
Page 8, figure 1.
Suppose Vgg is a low voltage or even ground.
If Vdd is switched on, the voltage on both sides of the capacitor is low, so the mosfet turns on.
But the fast rising of Vout causes a current through the capacitor towards the gate. The voltage on both sides of the capacitor is still the same, until the capacitor is slowly charged. That works agains the gate voltage, causing a slower rise of Vout.

I don't know what else I can make of it. I don't have the time to build a few circuits (that would be the way for me to understand it). Perhaps someone else can shine some light on this.
« Last Edit: March 19, 2013, 03:11:46 pm by Erdin » Logged

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Using N-channel on high side would be possible if a voltage for the gate is available that is higher than the source or the drain. Like I wrote, that is almost never the case.

That I don't have, so that removes that possibility.

As for the PMOS application, yes - let's hope some others can chime in here too...

Cheers!
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