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Topic: Using 74HC165N w/ SPI (Read 975 times) previous topic - next topic

CrossRoads

http://www.ti.com/lit/ds/symlink/sn74hc165.pdf

// capture data
digitalWrite(shPin, LOW); // 74HC165 pin 1
digitalWrite(shPin, HIGH);

// read in data
digitalWrite(ssPin, LOW); // 74HC165 pin 15 (but with no Output enable, can be low all the time)
incomingByte = SPI.transfer(0); // shift-in register output connects to arduino's MISO pin
digitalWrite(ssPin, HIGH);
Designing & building electrical circuits for over 25 years. Check out the ATMega1284P based Bobuino and other '328P & '1284P creations & offerings at  www.crossroadsfencing.com/BobuinoRev17.
Arduino for Teens available at Amazon.com.

BiohazrD

#6
Mar 22, 2013, 08:38 pm Last Edit: Mar 22, 2013, 08:43 pm by BiohazrD Reason: 1

http://www.ti.com/lit/ds/symlink/sn74hc165.pdf

// capture data
digitalWrite(shPin, LOW); // 74HC165 pin 1
digitalWrite(shPin, HIGH);

// read in data
digitalWrite(ssPin, LOW); // 74HC165 pin 15 (but with no Output enable, can be low all the time)
incomingByte = SPI.transfer(0); // shift-in register output connects to arduino's MISO pin
digitalWrite(ssPin, HIGH);



I'm confused, isn't pin 15 output enable? I mean, they call it CLK INH, but when it's pulled low, the register begins to output data.

I've seen some examples of pin 15 always tied low, and SS set to SH/LD.

CrossRoads

Pin is not output enable - it is Clock Inhibit. It needs to be low to allow the CLK line to toggle within the chip.  Look at the datasheet.
The output pin is active all the time.

"While SH/LD is low, the parallel inputs to the register are enabled independently of the levels of the CLK, CLK INH, or serial (SER) inputs."
See the timing diagram on page 3.
Designing & building electrical circuits for over 25 years. Check out the ATMega1284P based Bobuino and other '328P & '1284P creations & offerings at  www.crossroadsfencing.com/BobuinoRev17.
Arduino for Teens available at Amazon.com.

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