next topic »

[on:]

I'm currently trying to create a project that can read and write to lots of different GPIO pins. I currently have the output working using a series of 74HC595s on SPI and wanted to use the same SPI setup with a different SS conencted to the 74HC165Ns. But for the life of me, I can't figure out what pin on the 165 would be the SS pin, and how I would chain them together.

Any ideas?

[Reply #1 on:]

If SS is slave select then use pin 15 the CE or chip enable pin.

[Reply #2 on:]

Pin 15 - the "CE" pin.

[Reply #3 on:]

So in that case would I use MOSI to SH/!LD? Write a 0 to load the values and then set SS (CE) to low and begin reading on MISO?

[Reply #4 on:]

No, you need to pulse PL and then clock the data in. So you could do this by hand before letting the SPI read it in.

[Reply #5 on:]

http://www.ti.com/lit/ds/symlink/sn74hc165.pdf

// capture data
digitalWrite(shPin, LOW); // 74HC165 pin 1
digitalWrite(shPin, HIGH);

// read in data
digitalWrite(ssPin, LOW); // 74HC165 pin 15 (but with no Output enable, can be low all the time)
incomingByte = SPI.transfer(0); // shift-in register output connects to arduino's MISO pin
digitalWrite(ssPin, HIGH);

[Reply #6 on:]

http://www.ti.com/lit/ds/symlink/sn74hc165.pdf

// capture data
digitalWrite(shPin, LOW); // 74HC165 pin 1
digitalWrite(shPin, HIGH);

// read in data
digitalWrite(ssPin, LOW); // 74HC165 pin 15 (but with no Output enable, can be low all the time)
incomingByte = SPI.transfer(0); // shift-in register output connects to arduino's MISO pin
digitalWrite(ssPin, HIGH);

I'm confused, isn't pin 15 output enable? I mean, they call it CLK INH, but when it's pulled low, the register begins to output data.

I've seen some examples of pin 15 always tied low, and SS set to SH/LD.

[Reply #7 on:]

Pin is not output enable - it is Clock Inhibit. It needs to be low to allow the CLK line to toggle within the chip.  Look at the datasheet.
The output pin is active all the time.

"While SH/LD is low, the parallel inputs to the register are enabled independently of the levels of the CLK, CLK INH, or serial (SER) inputs."
See the timing diagram on page 3.