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Author Topic: Arduino based PCB - layout, crystal and planes  (Read 1148 times)
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Hej everyone,

maybe you can give me an advice regarding my current project, a small midi controller box with an ATmega328, 8 rotary pots, digital communication (serial / midi protocoll) and some infrastructure.

Before I designed the appended PCB, I tried to learn about proper PCB-design via google, this forum etc. So I am not an "an academically educated electrical engineer", but a hobbyist who wants to have good results and often is more or less confused about the sometimes contradictory statements about good PCB-design one can find, especially when it comes to grounding, ground planes, decoupling, etc.

Long story short: What do you think about this PCB-design? I.e. a friend of mine mentioned the planes are much too big, this could result in a not working crystal.
Note: The top layer contains the ground plane, the bottom layer the +5V plane.

greets & thanx,
Marcel



* MBaseKontrol_V1_2.jpg (300.86 KB, 392x597 - viewed 33 times.)

* MBaseKontrol_V1_TOP.jpg (94.35 KB, 396x609 - viewed 19 times.)

* MBaseKontrol_V1_BOT.jpg (111.52 KB, 396x609 - viewed 20 times.)
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It is hard to tell without the schematic.
Ground plane under the crystal can be a problem.
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Ground plane under the crystal can be a problem.

Additional capacitance?
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... here we go:


* MBaseKontrol_V1_Schematik.jpg (508.97 KB, 1653x1169 - viewed 39 times.)
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Thank you! I will make the left ground trace smaller / remove the plane below the crystal.

Anyone any further advices? smiley

greets,
Marcel
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You need to add a 0.1uF capacitor between Avcc and ground. I'm not sure whether C6 (between Vref and ground) is whrthwhile, the datasheet doesn't mention putting a capacitor there, although I can see that it might help filter out power supply noise.

PS - you should join up the ground plane traces much more. You seem to be trying to avoid having lops in the ground plane, but there is no need to do that. Aim to put ground plane almost everywhere there isn't anything else. I doubt that ground place under the crystal would be an issue, as the traces to the XTAL1 and XTAl2 pins are short and thin; but if it worries you, leave it out there.
« Last Edit: March 30, 2013, 03:14:00 am by dc42 » Logged

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You Want ground plane under the cap, try for both sides if possible. See attached.

* Atmel AVR042 AVR Hardware Design Considerations.pdf (236.19 KB - downloaded 10 times.)
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On a side note, you need a good place to get these manufactured! I used seeedstudio for mine, and the boards came out pretty decent, especially for the price (although silkscreen wasn't amazing).

I've reviewed the service here, check it out:
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You need to add a 0.1uF capacitor between Avcc and ground.
Thanx! Yeah, this is shown in the datasheet on page 258 ... I just forgot to add it ...

Quote
I'm not sure whether C6 (between Vref and ground) is whrthwhile, the datasheet doesn't mention putting a capacitor there, although I can see that it might help filter out power supply noise.
The datasheet on page 250 says "The internal voltage reference may thus be decoupled by an external capacitor at the AREF pin to improve noise immunity" ... so I did. smiley

Quote
PS - you should join up the ground plane traces much more. You seem to be trying to avoid having lops in the ground plane, but there is no need to do that. Aim to put ground plane almost everywhere there isn't anything else.
I tried to seperate analog and digital ... I realized there is no (major) analog (load), but with my limited knowledge I try to do it as "perfect" as possible for me. I saw some PCBs with copper all over - i.e. the UNO board. But is this really the "correct way"?

You Want ground plane under the cap, try for both sides if possible. See attached.
Thank you for posting that interesting document - I didn't know yet. But: I can't read / conclude which cap you exactly mean. (?)

On a side note, you need a good place to get these manufactured! I used seeedstudio for mine, and the boards came out pretty decent, especially for the price (although silkscreen wasn't amazing).
I already checked out seedstudio and also heard good things about, but as I am located in germany I will try someone nearer.

greets,
Marcel
« Last Edit: March 30, 2013, 05:39:10 pm by BruceX » Logged

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Under the cap - I meant under the crystal.
See all the red, and all the blue? That's all ground layer. Maximize it.
Sometimes you can move a trace over to let ground in between traces to expand into an area.
Sometimes you need to add a via Named GND to connect the top & bottom layer to let more ground in.


* Thruhole_layout_top.png (42.69 KB, 868x457 - viewed 22 times.)

* Thruhole_layout_bottom.png (40.29 KB, 868x457 - viewed 14 times.)
« Last Edit: March 30, 2013, 06:08:26 pm by CrossRoads » Logged

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Hi,

As already mentioned try to use supply or ground planes, they make routing more easy and also shield the lanes.

I manufactured my pcbs at eurocircuit. They're fast and even offer Support in german Language.
Also, they do have some interisting Manuals about layouting. Give it a try!


Grüße aus Bremen

-tsaG
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Much thanx (and respect) to you. But also some contradictions here, one advices "ground planes under a crystal can be a problem", another one says "ground under crystal necessary / ground plane all over" while a friend of mine tells me "your planes are too big" ... finally I conclude: For this try I leave it as it is (besides I added the 0.1UF cap as suggested by dc42), I already have planes (ground on top layer, +5V on bottom) and hope this works. smiley

And also very nice for me: The linked application note of ATMEL (posted by CrossRoads) - I didn't even know about them. Will read more of them in the future!

regards,
Marcel
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Another benefit of maximum ground plane is that minimal etching is done to remove material during the board manufacture.
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Hallo Marcel

You are quite right in feeling frustrated with so many contradictions regarding the ground plane under the crystal. Perhaps this reply could put your concerns to rest and I will attempt to keep it as simple as possible.

We note  that the piezoelectric crystal is seald within a metallic "can" which can be classified as a "Faraday cage". Therefore any electrical fields inside the "can" are unable to interact with the outside world. As a result of this, the presence of a ground plane under the crystal will have no effect on its performance.

So now we have to look for other variables that can affect the performance of the crystal. I want you to look at the attached figure.

In Figure A, the crystal interacts with the outside world by means of electrical tracks to the microcontroller. Also we note that the crystal has 22pF on each leg. Lets call these capacitors CL1 and CL2. These capacitors are reccomended by the manufacturer and add LOAD capacitance to the crystal. The size of the LOAD capacitance determines how much the frequency of the crystal is PULLED. The amount by wich a crystal is pulled is called the PPM value or Parts Per Million.

For example, if a 16MHz crystal is pulled off by +100PPM, it means that:
for every 1 million Hertz (1MHz), the frequency is pulled off by +100Hertz
therefore for 16 million Hertz (16MHz), the frequency is pulled off by +1600Hertz

We now have to introduce one final variable. Its the stray capacitance Cs. This stray capacitance Cs (in pF) is calculated by  the formula Cs= (AE)/d 

where A is the area of the track that joins the the pin of the crystal to the leg of the micro
(Area A = W x L)
E is the dielectric constant of the printed circuit board (typically = 4 for fiberglass)
d is the hight of the printed cricuit board (I assume 1.6mm)   

So to sum it up nicely, the total load capacitance is:

C Load   = [ (CL1 x CL2)/(CL1 +CL2) ] + Cs


Once you have the value of C Load, you use the crystal data sheet to see by how many PPM the crystal will be PULLED as shown in figure B.

The point I want to stress is that the value of C Load is in part dependent on the stray capacitance Cs.
If you take away the ground plane, Cs will diminish to zero because the signal tracks at the bottom layer will have no copper ground plane to interact with.

Lets put some numbers to quantify this. Assume that we pour a ground plane on top and we have a track of width 1mm and length 10mm. Assume the dielectric constant "E" = 4 and the height of the substrate "d" is 1.6mm. The stray capacitance is:

Cs= (AE)/d =(WxL)(E)/d = (1x10)(4)/(1.6) = 25pF


Now we complete the whole loading capacitance equation:

C Load   = [ (CL1 x CL2)/(CL1 +CL2) ] + Cs

C Load   = [ (22 x 22)/(22 +22) ] + 25

C Load = [11] + 25

C Load = 36pF

Looking at the graph in figure B we see that the 16MHz crystal is pulled off by -300PPM or -4.8KHz to be exact
 
To conclude, we can say that the ground plane DOES have an effect on the crystal's frequency of operation. The ground plane will introduce stray capacitance Cs which in turn will affect the PPM value. The question you have to answer is whether the PPM deviation of the crystal falls with in your operational specifiations. 





* Stray Capacitance.JPG (75.9 KB, 960x1200 - viewed 18 times.)
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Very nice explanation DigitalRS.  It is good to know there are clear-speak teachers out there.  I have known CV probe Sr. Engineers that took two days to explain what you did in a single post.  Thank you for dropping in.
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