Ok. I merged the SA-1 BW-RAM changes from the Enhanced sketch with Oatburner's $2226 register change and managed to get it working. The code still isn't perfect as the initial SRAM byte needs to be rewritten at the end of the write. It works and is more accurate than the original version that was in sanni's sketch.
Here's the fixed SA-1 BW-RAM Write Code for sanni's current V30I sketch:
void writeSRAM (boolean browseFile) {
...
// SA1
else if (romType == SA) {
long lastByte = (long(sramSize) * 128);
// Enable CPU Clock
clockgen.set_freq(357954500ULL, SI5351_CLK1);
clockgen.output_enable(SI5351_CLK1, 1);
// Direct writes to BW-RAM (SRAM) in banks 0x40-0x43 don't work
// Break BW-RAM (SRAM) into 0x2000 blocks
byte lastBlock = 0;
lastBlock = lastByte / 0x2000;
// Writing SRAM on SA1 needs CS(PH3) to be high
// PORTH |= (1 << 3);
// Setup BW-RAM
// Set 0x2224 (SNES BMAPS) to map SRAM Block 0 to 0x6000-0x7FFF
writeBank_SNES(0, 0x2224, 0);
// Set 0x2226 (SNES SBWE) to 0x80 Write Enable
writeBank_SNES(0, 0x2226, 0x80);
// Set 0x2228 (SNES BWPA) to 0x00 BW-RAM Write-Protected Area
writeBank_SNES(0, 0x2228, 0);
delay(1000);
// Use $2224 (SNES) to map BW-RAM block to 0x6000-0x7FFF
// Use $2226 (SNES) to write enable the BW-RAM
byte firstByte = 0;
for (byte currBlock = 0; currBlock < lastBlock; currBlock++) {
// Set 0x2224 (SNES BMAPS) to map SRAM Block to 0x6000-0x7FFF
writeBank_SNES(0, 0x2224, currBlock);
// Set 0x2226 (SNES SBWE) to 0x80 Write Enable
writeBank_SNES(0, 0x2226, 0x80);
for (long currByte = 0x6000; currByte < 0x8000; currByte += 512) {
myFile.read(sdBuffer, 512);
if ((currBlock == 0) && (currByte == 0x6000)) {
firstByte = sdBuffer[0];
}
for (int c = 0; c < 512; c++) {
writeBank_SNES(0, currByte + c, sdBuffer[c]);
}
}
}
// Rewrite First Byte
writeBank_SNES(0, 0x2224, 0);
writeBank_SNES(0, 0x2226, 0x80);
writeBank_SNES(0, 0x6000, firstByte);
// Disable CPU clock
clockgen.output_enable(SI5351_CLK1, 0);
...
}
...
}
Here's the fixed SA-1 BW-RAM Erase Code:
boolean eraseSRAM (byte b) {
...
// SA1
else if (romType == SA) {
long lastByte = (long(sramSize) * 128);
// Enable CPU Clock
clockgen.set_freq(357954500ULL, SI5351_CLK1);
clockgen.output_enable(SI5351_CLK1, 1);
// Direct writes to BW-RAM (SRAM) in banks 0x40-0x43 don't work
// Break BW-RAM (SRAM) into 0x2000 blocks
// Use $2224 to map BW-RAM block to 0x6000-0x7FFF
byte lastBlock = 0;
lastBlock = lastByte / 0x2000;
// Writing SRAM on SA1 needs CS(PH3) to be high
// PORTH |= (1 << 3);
// Setup BW-RAM
// Set 0x2224 (SNES BMAPS) to map SRAM Block 0 to 0x6000-0x7FFF
writeBank_SNES(0, 0x2224, 0);
// Set 0x2226 (SNES SBWE) to 0x80 Write Enable
writeBank_SNES(0, 0x2226, 0x80);
// Set 0x2228 (SNES BWPA) to 0x00 BW-RAM Write-Protected Area
writeBank_SNES(0, 0x2228, 0);
delay(1000);
// Use $2224 (SNES) to map BW-RAM block to 0x6000-0x7FFF
// Use $2226 (SNES) to write enable the BW-RAM
for (byte currBlock = 0; currBlock < lastBlock; currBlock++) {
// Set 0x2224 (SNES BMAPS) to map SRAM Block to 0x6000-0x7FFF
writeBank_SNES(0, 0x2224, currBlock);
// Set 0x2226 (SNES SBWE) to 0x80 Write Enable
writeBank_SNES(0, 0x2226, 0x80);
for (long currByte = 0x6000; currByte < 0x8000; currByte += 512) {
for (int c = 0; c < 512; c++) {
writeBank_SNES(0, currByte + c, b);
}
}
}
// Rewrite First Byte
writeBank_SNES(0, 0x2224, 0);
writeBank_SNES(0, 0x2226, 0x80);
writeBank_SNES(0, 0x6000, b);
// Disable CPU clock
clockgen.output_enable(SI5351_CLK1, 0);
}
...
}