From the datasheet:
22.5.2 Bit Rate Generator Unit
This unit controls the period of SCL when operating in a Master mode. The SCL period is controlled by settings in
the TWI Bit Rate Register (TWBR) and the Prescaler bits in the TWI Status Register (TWSR). Slave operation
does not depend on Bit Rate or Prescaler settings, but the CPU clock frequency in the Slave must be at least 16
times higher than the SCL frequency. Note that slaves may prolong the SCL low period, thereby reducing the average
TWI bus clock period. The SCL frequency is generated according to the following equation:
SCL frequency = (CPU Clock frequency)/(16 + 2 x (TWBR) PrescalerValue))
• TWBR = Value of the TWI Bit Rate Register.
• PrescalerValue = Value of the prescaler, see Table 22-7 on page 236."
I don't IDE access here, so I don't know how any of that meshes with:
#define TWI_FREQ 100L
This little tool is great for looking at this kind of thing:http://www.saleae.com/logic
Shows you the signals, can make fine time measurements, and it also decodes the bursts of data to show the byte being transmitted with every burst.
Save yourself up some money and pick one up if you can.
I used mine recently to fine tune some SPI.transfer code & confirm my code was able to spit out data really fast!
SPI can send data out with 8 MHz clock. 8 bits, 2 clock cycles/bit = 1uS per byte - I had 41 bytes going in 46uS, so pretty close to as fast as possible.