Many instructions, including multiplying, are single cycle. Separate data and instruction buses (Harvard architecture) allow simultaneous data and instruction accesses to be performed. Also, up to two instructions can be fetched in one cycle (they share the same memory space). Thanks to the Thumb-2 instruction set feature, there is no need to switch between 32 and 16 instructions that can be used together in one operation state (no state switching overhead). In other words, saving both execution time and instruction space give the Cortex-M3 processor higher performance efficiency.