1. does the hardware behind analogRead need to be blocking?
I don't understand what you're asking. The mega168 only has one ADC, which means you can only be performing a conversion on one channel at a time. While the conversion is going on, the ADC hardware is by definition busy, but this does not occupy the processor in any way.
2. Does the performance of an analog read improve with a faster clock rate?
The ADC has its own clock (a prescaled version of the system clock). To get maximum resolution (i.e. 10 bits), the ADC clock must be between 50 and 200 kHz. If you don't need maximum resolution, you can run the ADC faster than 200 kHz, but the faster it is, the lower the resolution. Note that the analog-to-digital conversion takes 13 ADC clock cycles while the ADC is running normally and 25 clock cycles to initialize the ADC and perform the first conversion. This means that if you want maximum resolution, you will have a sample rate of around 15 kHz.
3. and if(!1) can you gang the analog read pins together and not have the reads interfere with each other if triggered at different (overlapping) times?
No. The ADC spends nearly its entire conversion time measuring the voltage on the channel for which it is set.
I'm just wondering because it seems that if you put the fastest crystal the atmega can stand (say 32mhz)
The fastest the mega168 can run (according to its spec) is 20 MHz. If you run it faster than this it might work (or seem
to work, but it is out of spec and could lead to all sorts of obscure problems.