the cut-off frequency

Do you know what that means? The frequency where the capacitave reactance equal the resistance is the 3dB point. It is not the point where no more signal is let through.

I do understand that, at least to a certain extent (I have no doubt I'm ignoring a lot of factors that play a role on that). I''ve plotted the bode diagram of that and I wouldn't be concerned if it wasn't right in the middle of my frequency range of interest. At 50Hz I will have around 10dB which, if I understand the meaning of that value, I'll have 1:10 of the original voltage... back to 250mV.

Please take in consideration my goal is to measure frequence and amplitude of two sine waves in [50,200]Hz

To me that pair of components represent an issue, unless I'm mistaken in my reasoning.

If this is not good enough Then you are better off using a larger capacitor than lowering the resistance this is to make the vertuial ground more robust than it would be at 10K. But you can up it to 10K. If you want.

What is the difference? If I increase the voltage divider resistors value I will lower the current in the Aduino side of the circuit (don't know about other effects), I don't know the effect of increasing the capacitor value though