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Topic: Merging multiple gerbers for multi-panel project (Read 472 times) previous topic - next topic

avrguy

I'm about to order multiple designs in one batch and I needed to
merge the gerbers into one single gerber. I did some searching
and found that others have used a free program called GerbMerge:
http://claymore.engineer.gvsu.edu/~steriana/Python/gerbmerge/index.html

I saw a lot of posts that said it was hard to use and several people
had given up. Once I had GerbMerge installed I had my merged
Gerbers ready to go in about 15 minutes. I thought I'd document the
steps to help anyone that needs to use it. I'm using it on linux (FC10) but
I assume windows would be similar.

-- Install GerbMerge and it's prerequisites.
-- Copy your gerbers to a folder, I named them pcb1 and pcb2.
-- Setup a config file, I used panel.cfg, I'll copy it in below.
-- run GerbView: gerbview panel.cfg

The sample config file has a lot of comments that describe each
option. I removed them to make it easier to read. I'm using GP
and their panel size is 14.5 x 10. Be sure to edit this in the config
file and also the number of boards you want. You also need a
board outline layer .bor that I have not supplied separately in the
past, it's been on the top silk later.

I used the automatic placement option in GerbView and it seemed to
be as good as I could have done manually.

Here is the panel.cfg file:

Code: [Select]
[DEFAULT]

projdir = .

MergeOut = merge1

[Options]

#ToolList=proj1.drl
#ExcellonDecimals = 4
CutLineLayers = *topsilkscreen,*bottomsilkscreen
CropMarkLayers = *topsilkscreen,*bottomsilkscreen
FabricationDrawingFile = %(mergeout)s.fab
#FabricationDrawingText = %(projdir)s/fabdwg.txt
ExcellonLeadingZeros = 0
OutlineLayerFile = %(mergeout)s.oln
ScoringFile = %(mergeout)s.sco

# panel size here:

PanelWidth = 14.5
PanelHeight = 10

LeftMargin   = 0.1
RightMargin  = 0.1
TopMargin    = 0.1
BottomMargin = 0.1

XSpacing = 0.125
YSpacing = 0.125

CutLineWidth = 0.01

CropMarkWidth = 0.01

AllowMissingLayers = 0

DrillClusterTolerance = 0.002

MinimumFeatureSize = *topsilkscreen,0.008,*bottomsilkscreen,0.008

[MergeOutputFiles]
Prefix = %(mergeout)s

*TopLayer=%(prefix)s.cmp
*BottomLayer=%(prefix)s.sol
*TopSilkscreen=%(prefix)s.plc
*BottomSilkscreen=%(prefix)s.pls
*TopSoldermask=%(prefix)s.stc
*BottomSoldermask=%(prefix)s.sts
Drills=%(prefix)s.xln
BoardOutline=%(prefix)s.bor
ToolList = toollist.%(prefix)s.drl
Placement = placement.%(prefix)s.txt

# options below here are for each PCB in your design

# this is for PCB 1

[pcb1]

Prefix=%(projdir)s/pcb1

*TopLayer=%(prefix)s.cmp
*BottomLayer=%(prefix)s.sol
*TopSilkscreen=%(prefix)s.plc
*BottomSilkscreen=%(prefix)s.pls
*TopSoldermask=%(prefix)s.stc
*BottomSoldermask=%(prefix)s.sts
Drills=%(prefix)s.drd
BoardOutline=%(prefix)s.bor


Repeat = 3


# this is for PCB 2

[pcb2]

Prefix=%(projdir)s/pcb2

*TopLayer=%(prefix)s.cmp
*BottomLayer=%(prefix)s.sol
*TopSilkscreen=%(prefix)s.plc
*BottomSilkscreen=%(prefix)s.pls
*TopSoldermask=%(prefix)s.stc
*BottomSoldermask=%(prefix)s.sts
Drills=%(prefix)s.drd
BoardOutline=%(prefix)s.bor


Repeat = 3





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