So is the purpose of this so that the A/D conversion is performed in a quieter condition then normal non-sleeping condition?
Exactly. I've notice some difference on the ATmega processors. There seems to be less jitter in the least-significant bit. I've notice a huge difference on the ATtiny processors. The values are rather erratic in "polling mode" but rock solid in "noise reduction mode".
I have noticed that on the code I've posted that if I perform just one read of the bandgap voltage it has not settled down to a stable count value.
My 168 and 328 processors behave the same way. The first reading after switching ADMUX to "measure the bandgap" is garbage.
Three reads is OK, within a count or two, and four has the same stable count reading that stays the same no matter how long the function continues.
About the same here. I usually have a short time delay between readings so, in my case, the readings are stable by the third one.