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Topic: Transmit interupt causes reset (Read 672 times) previous topic - next topic

feros

Jul 02, 2009, 02:39 am Last Edit: Jul 02, 2009, 02:40 am by axlan Reason: 1
I've been trying to rewrite the Hardware serial core files to make transmit buffered and interrupt driven. I got my code to compile, but have had weird issues with the interrupts. When I tried to use the data ready interrupt it seems to work fine. I can get the examples to compile and run correctly. Unfortunately I need to use the TWI. Somehow my changes cause the wire library to hang in twi_writeTo at the line
Code: [Select]
// wait for write operation to complete
     while(wait && (TWI_MTX == twi_state)){
       continue;
     }

My guess is that the USART interrupt is somehow interfering with the TWI one. I have no idea why this should be the case.

When I try to use the transmit complete interrupt the uC resets which seems to imply the compiler isn't including the interrupt properly.  

I enable the interupts by adding   sbi(*_ucsrb, _txcie); and the appropriate code to set the variables after
 sbi(*_ucsrb, _rxen);
 sbi(*_ucsrb, _txen);
 sbi(*_ucsrb, _rxcie);

and use the SIG_USART_TRANS vector.

I'm using the atmega328p.

Anyone have any insight into what might cause these errors? I'll post the complete code later, but it's pretty long. If someone has already written code to do this that would be appreciated as well.

RuggedCircuits

I'm surprised you're using the SIG_USART_TRANS vector, as I don't see that as a defined vector in the iom328p.h file. Try renaming that to USART_TX_vect (or really, USART_UDRE_vect would be better).

feros

#2
Jul 02, 2009, 10:09 am Last Edit: Jul 02, 2009, 11:26 am by axlan Reason: 1
Quote
I'm surprised you're using the SIG_USART_TRANS vector, as I don't see that as a defined vector in the iom328p.h file. Try renaming that to USART_TX_vect (or really, USART_UDRE_vect would be better).


I was trying to stay consistent with the SIG_USART0_RECV, but you're right, guess I should use a redefinition if I want to be consistent. Also USART_UDRE_vect is the data ready interrupt I mention earlier that has the even weirder problem of interfering with the TWI interrupt.

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