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Topic: Input- and Output-Level Specifications of 1.8V Core of SAM3X8E Microcontroller (Read 488 times) previous topic - next topic

GolamMostafa

Pupils frequently ask about the subject matter; but, the data sheets (Table 45-2) of SAM3X8E has only given: VDDCORE = 1.8V. What are there about other parameters: VIL, VIH, VOL, VOH, IIL, IIH, IOL, and IOH for the 1.8V Core.

The poster has prepared the following diagram for VIL, VIH, VOL, and VOH based on this article (Figure 1) and considering the Core as an LVC Logic. Comments, corrections, and additions are  highly appreciated.



Definitions:
VIL: Maximum voltage at the input of the gate, which stays below the forbidden zone and is reliably recognized as Logic-L state.

VIH: Minimum voltage at the input of the gate, which stays above the forbidden zone and is reliably recognized as Logic-H state.

VOL: Maximum voltage at the output of the gate, which stays below the forbidden zone and is reliably recognized as Logic-L state by the driven gate.

VOH: Minimum voltage at the output of the gate, which stays above the forbidden zone and is reliably recognized as Logic-H state by the driven gate.

IIL: Maximum current exiting from an input terminal of the driven gate, which is at Logic-L state because of its connection with the Low-state output of the driver gate.

IIH: Maximum current entering into an input terminal of the driven gate, which is at Logic-H state because of its connection with the High-state output of the driver gate.

IOL: Maximum current, which the output transistor of the driver gate will be sinking from the driven gates when the output of this driver gate is at Logic-L state.

IOH: Maximum current, which the output stage of the driver gate will be delivering to the driven gates when the output of this driver gate is at Logic-H state.

westfw

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What are there about other parameters: VIL, VIH, VOL, VOH, IIL, IIH, IOL, and IOH for the 1.8V Core.
Why should they be specified, when they're not exposed on any pins accessible to the user?

GolamMostafa

If I have to answer on behalf of the pupils, I need to wait to hear from them why they are asking me this question.

I have a reason to know, which is to compute the 'Worst-case Noise Margins (NML and NMH)' while the Core runs  at 4 - 84 MHz speed and creates substantial amount of electrical noise. Noise Margin is a figure, which quantifies the maximum level of environmental noise signal that can be tolerated by the electrical/logic gate. This means:

VOL + Noise <= VIL
VOH + Noise => VIH

The SAM3X8E data sheet has not specified these parameters.  

Based on the values of VIL, VIH, VOL, and VOH:

High State Noise Margin, NMH = VOH - VIH = 1.35 - 1.17 = 0.18V
Low State Noise Margin, NML   = VIL - VOL = 0.63 - 0.45 = 0.18V



Figure-1: Illustrating the noise margin situation of SAM3X8E MCU

The next question may arise as: SAM3X8E is working fine with the stated noise margins. Why is there the need of knowing/computing the noise margin figures?  

The value helps us comparing the noise margin level of ARM (typical 0.18V) with 5V-CMOSHC (typical NML/NMH = 0.6V/0.7), and then to appreciate the fabrication technology that makes ARM working with such a low NM value!

My interest is pure academic.

westfw

There's also no reason for the internal circuitry to maintain the same sort of voltage thresholds (or hysteresis) that is expected from external pins.  (This probably shows up most in lack of symmetry of current drive capabilities.  External CMOS outputs are usually expected to be able to source or sink similar currents, but I believe that the physics say that NMOS transistors will sink more current than PMOS transistors of the same size will source...)

I would think that there should be some generic articles on the topic of lowered supply voltages in CMOS logic circuits.  Lowering the voltage is a key part of increasing speed and decreasing power consumption, and chips like desktop Intel CPUs (Vcore ~= 1.2V) and FPGAs (Vcore < 0.8V) have been pushing the voltages down for a long time now.
Perhaps This TI Guide on their 74AUC "Ultra Low Voltage Logic"

GolamMostafa

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There's also no reason for the internal circuitry to maintain the same sort of voltage thresholds (or hysteresis) that is expected from external pins.
Very interesting and inspiring information.

Traditionally, we (the maintenance/training engineers, amateur designers, and later teachers) have been bearing the mind-set of seeing the electronics logic gates from 5-V TTL/CMOS perspective. This is the first time we (myself and my pupils) are playing with 1.8V Core and 3.3V IO. Because the Arduino DUE is readily available and comparatively not so expensive, we find here a lot of opportunities to design/interfacing hand-made logic sifters rather than using factory-made dedicated logic sifters.  

The data sheet of SAM3X8E is not organized and informative as the ATmega328P is. As we are proceeding with the studies and experiments of Arduino DUE, we are faced with many many conceptual questions. It is a matter of happiness that the DUE Members try their best to present rational opinions along with additional reading materials.

@wstfw

Your question of Post#1, from my view point, deserves much better answer and explanation/discussion than what I have presented in Post#2. I hope that other members including you may present some discussion on this issue.

BTW: Increasing speed: Does it refer to the lower time in the transition of H-to-L/L-to-H or Clock Period or both?

westfw

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Increasing speed: Does it refer to the lower time in the transition of H-to-L/L-to-H or Clock Period or both?
Both, I think.  CMOS logic tends to be limited by the gate capacitance of the MOSFETs, and the time to charge or discharge the gates till they hit their thresholds.  A smaller voltage range means less energy to move around, so it happens faster for a given drive current.  (I mean, the "clock period" is just a result of the internal H/L transition speeds...)
Even in the old days, faster logic tended to have smaller voltage swings.  The famous ECL logic family is old and very fast, and has IO voltage swings of about 0.8V (according to wikipedia.)  The latest version seems to be from 1987, and has a switching speed of ~500ps!

GolamMostafa

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The famous ECL logic family is old and very fast, and has IO voltage swings of about 0.8V (according to wikipedia.)
Yes! The swing voltage is an important factor that contributes to lower switching time (the average propagation delay). In the following Table, we observe that the ECL is still the fastest logic gate. We also observe that the ECL has the lowest output swing voltage.





A practical ECL-OR Gate built in Lab to study its various non-saturating characteristics:  



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