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Topic: Zero RTC - getting a 1Hz interrupt (Read 1 time) previous topic - next topic

Phil-D

Hi David

The startup.c file has this in the comments, which seems to suggest the external crystal should be the source for the main 48MHz clock.  So I'm not sure it's by design that the external clock isn't being used, it seems the intention was to use the external crystal as the reference for the DFLL48M which then clocks generator 0 which runs the CPU at 48MHz.

From the code I'm not sure where it is going wrong however.


Code: [Select]

1) Enable XOSC32K clock (External on-board 32.768Hz oscillator), will be used as DFLL48M reference.
2) Put XOSC32K as source of Generic Clock Generator 1
3) Put Generic Clock Generator 1 as source for Generic Clock Multiplexer 0 (DFLL48M reference)
4) Enable DFLL48M clock
5) Switch Generic Clock Generator 0 to DFLL48M. CPU will run at 48MHz.
6) Modify PRESCaler value of OSCM to have 8MHz
7) Put OSC8M as source for Generic Clock Generator 3


Regards

Phil

MartinL

#16
Jun 23, 2018, 04:36 pm Last Edit: Jun 23, 2018, 04:36 pm by MartinL
Hi Phil,

The external 32.768kHz crystal is used as the source to drive the SAMD21's Digital Frequency Locked Loop (DFLL48M) that multiplies the frequency up to 48MHz.

Here's the multiplier in the "startup.c" file:

Code: [Select]
SYSCTRL->DFLLMUL.reg = SYSCTRL_DFLLMUL_CSTEP( 31 ) | // Coarse step is 31, half of the max value
                       SYSCTRL_DFLLMUL_FSTEP( 511 ) | // Fine step is 511, half of the max value
                       SYSCTRL_DFLLMUL_MUL( (VARIANT_MCK + VARIANT_MAINOSC/2) / VARIANT_MAINOSC ) ; // External 32KHz is the reference

The 32.768kHz frequency is mulitplied up by:

(VARIANT_MCK + VARIANT_MAINOSC / 2) / VARIANT_MAINOSC =

(48MHz + 32.768kHz / 2) / 32.768kHz = 1465

32.768kHz * 1465 = 48005120Hz = 48MHz

The integer arthimetic used by the multiplier introduces a 107ppm error to the 48MHz clock frequency, in addition to the crystal's ±20ppm.

Kind regards,
Martin

Phil-D

Hi Martin

The problem seems to be I'm not sure it is working the way its intended.  If I short the crystal, the CPU carries on running (code in the loop carries on as normal), although the RTC does stop.  So the crystal is being used by the RTC, but the main clock doesn't seem to use the crystal, despite all indications in the startup that it should be, something seems to be wrong somewhere.

Regards

Phil






MartinL

Hi Phil,

It could be that the DFLL is playing a role in keeping the 48MHz clock alive, after the reference crystal has been shorted.

Have you tried shorting the crystal while powering up the board, to see if the sketch still runs? This should prevent the DFLL locking on to the reference during start-up.

Kind regards,
Martin

Phil-D

Hi Martin

Thanks, that seems to be the case indeed, the DFLL somehow keeps going just fine even though the crystal is stopped, but it fails to start if shorted at power on.

The other test I did was in the startup.c file was remark out the line that enabled the external 32K clock, and it fails to then run any code.

Regards

Phil



MartinL

#20
Jun 25, 2018, 12:15 pm Last Edit: Jun 25, 2018, 12:15 pm by MartinL
Hi Phil,

It's possible to check if the DFLL has lost its reference clock, by checking the DFLLRCS bit in the system control's PCLKSR status register, (0: running, 1: stopped):

Code: [Select]
SerialUSB.println(SYSCTRL->PCLKSR.bit.DFLLRCS);
Kind regards,
Martin

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