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Author Topic: SPI programming: how to "control" SCLK  (Read 2819 times)
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SITUATION:
I'm messing with SPI starting a few days ago. Btw, for anyone also interested in SPI-learning, here are two good references I found:
http://www.rocketnumbernine.com/2009/04/26/using-spi-on-an-avr-1/
http://www.gammon.com.au/forum/?id=10892

Anyway, so now, I'm using this knowledge to program the ADS1252 (an ADC that uses SPI).

CURRENT STATE:
In the case of the ADS1252, the datasheet says, to create a RESET on the ADC, I have to maintain SCLK as HIGH for a minimum of four ADC internal modulator's conversion cycles... which I calculated as approx 59 microseconds.
I'm a little confused regarding how one "controls" SCLK.

QUESTION 1:
How do I actually control SCLK, i.e., maintain it HIGH for 59 microseconds?
Perhaps, does something this simple work?:
digitalWrite(SCLKpin, HIGH); delaymicroseconds(59); digitalWrite(SCLKpin, LOW);

Or is it preferable to use timer-interrupts and so forth?

QUESTION 2:
And now, how would you do the same if using the Arduino "SPI" library? (http://www.arduino.cc/playground/Code/Spi)
It does not have any function to regulate the SCLK pin...
« Last Edit: March 31, 2011, 03:17:46 pm by giantsfan3 » Logged

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The first option would work, but you probably would have to reset the SPI interface on the Arduino. Never tried it myself, though...
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Use your first option, then when using the SPI functions just dont mess with SCK, MISO, MOSI and SS, they will work just as they should, but when not using the SPI functions you can do what ever you want with the pins, that precisely why there is the Slave Select.
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In the case of the ADS1252, the datasheet says, to create a RESET on the ADC, I have to maintain SCLK as HIGH for a minimum of four ADC internal modulator's conversion cycles... which I calculated as approx 59 microseconds.
I'm a little confused regarding how one "controls" SCLK.

Why do you want to do this? Do you have multiple ADS1252 chips? According to the datasheet "The normal state of SCLK is LOW; however, by holding SCLK HIGH, multiple ADS1252s can be synchronized.". 

For a single chip this shouldn't be necessary. However if you really have multiple chips conceivably you could do it with your suggested code of manually holding the SCLK line high for the specified time.

I would be doing this before initializing the SPI library, because that "hands over" control of the 3 SPI lines (MISO, MOSI and SCLK) to the hardware.

You may find this helpful:

http://www.gammon.com.au/forum/?id=10892

I did some research into SPI, including logic analyzer screenshots, showing exactly what the various lines are doing, and some example master/slave code.
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Thank you very much all. While the whole ADC reading thing still hasn't worked out, at least the writing to SCK pin, BEFORE using the SPI library methods, worked fine.
And Nick, thanks for your reply, but also for your website. I remember reading it, then lost the URL; fantastic tutorial, esp. the logic analyzer shots clarified much when I recently began learning about SPI.

There is a very interesting puzzle with the ADS1252 ADC I'm attempting to solve:
As you see in the datasheet (http://focus.ti.com/lit/ds/symlink/ads1252.pdf), the DRDY/DOUT pin on the ADS1252 has combined responsibility of DRDY signaling and DOUT transfer. Which makes it a challenge to know exactly WHEN to read the data out.
Thus, to solve this problem, the reason I'm holding SCK high is due to my approach to gaining control over the ADC (feel free to suggest a more direct foolproof way if you see one):

Here is a diagram first:
Code:
                          |----------------ONE CONVERSION CYCLE---------------------------|
ADC phase:                 |---------DRDY phase-----| |-------------DOUT phase--------|
DRDY/DOUT line state:      HIGH [------------------VARIOUS--------------------] LOW
arduino action:            |--delays doing nothing--|  |-clocks out data-| |-wait for rising-edge interrupt-|

In words...
By holding SCK high for more than 4 ADC conversion cycles (but less than 20), I reset the ADC, as stated in the datasheet.
...Therefore, at the instant the reset is released (i.e., when I bring SCK back to LOW again), I know that I will be at a precise known time on the timing diagram of DOUT/DRDY line.

Then, for each ADC conversion cycle, I simply wait for the interrupt (Rising edge on DRDY/DOUT line) that guarantees that a new DRDY phase  is starting (and thus a new conversion cycle, because each conversion cycle starts with a HIGH on the DRDY/DOUT line, and ends with a LOW, after DOUT finishes).

So, from the start of DRDY phase (also, start of conversion cycle), I delay for a time equal to the (datasheet-specified) period of the DRDY phase, at the end of which the DOUT phase begins.
At this point, I clock out the 3 bytes of data. After I'm done (I'll now be somewhere in the middle of DOUT phase, and thus the DRDY/DOUT is held LOW by the ADC), I again wait for a rising-edge interrupt for the next conversion cycle to begin, and so on.

The code I've written for this so far is not working (aaargh!) but I'm assume this is a good approach (it's based on my reading of a TI application note regarding the same ADC: http://focus.ti.com/lit/an/slaa242/slaa242.pdf)


Thoughts/suggestions?
« Last Edit: April 01, 2011, 03:26:47 am by giantsfan3 » Logged

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Again, do you have multiple ADS1252 chips? If not, I don't see why you need to fiddle with SCK at all, but I'll check on that fact first.

Thanks for the compliments about the web site. I find that by documenting stuff I have to look into it deeply enough that I also understand it myself.
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Hey Nick, Just one ADC at the moment. I see what you are saying about SCK.

Maintaining SCK line high can be used for three different commands with this ADC (I think this chip is designed to do as much control as possible without using ADC registers; that direct simplicity is sort of why I bought it):
--for synchronization in case of multiple ADCs, as you mentioned
--for power-down
--for reset (holding SCK high for between 4 and 20 conversion cycles)

I'm using it for the third option (reset), as part of the method I'm using to have good control of the timing processes of the DRDY/DOUT line; more details on that in my last post above.
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Oh OK. Can you please put the [ code ] tags around your timing diagram? It looks pretty hard to read otherwise. (Select it and use the "#" button on the button bar).
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Anyway, so now, I'm using this knowledge to program the ADS1252 (an ADC that uses SPI).

Just an observation here. The datasheet never says it uses SPI (I searched for the word). Also it refers to the control lines as CLK, SCLK and DOUT/DRDY. This is different to MOSI, MISO, SCK, SS.

It may be simpler to just use serial shifting in and out (if necessary) rather than trying to use the SPI hardware. By the sounds of it you may have to enable/disable the SPI interface to get these extra clock pulse widths. I note that the device operates at a wide range of frequencies. The recommended frequency for rejection of 50 and 60 Hz power-line hum is only 3.480kHz, which is not very fast.
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The application note mentions SPI - to comment more I would have to see your code.
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Hi Nick, Just a headsup: Things are working! (Sort of... not amazing precision, maybe because I'm using potentiometer as my "sensor"/voltage input to the ADC, but it's definitely recording increases and decreases appropriately at least, and all 24 bits are being output consistently.)
Will keep you posted with a summary.
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