Thank you very much all. While the whole ADC reading thing still hasn't worked out, at least the writing to SCK pin, BEFORE using the SPI library methods, worked fine.
And Nick, thanks for your reply, but also for your website. I remember reading it, then lost the URL; fantastic tutorial, esp. the logic analyzer shots clarified much when I recently began learning about SPI.
There is a very interesting puzzle with the ADS1252 ADC I'm attempting to solve:
As you see in the datasheet (http://focus.ti.com/lit/ds/symlink/ads1252.pdf
), the DRDY/DOUT pin on the ADS1252 has combined responsibility of DRDY signaling and DOUT transfer. Which makes it a challenge to know exactly WHEN to read the data out.
Thus, to solve this problem, the reason I'm holding SCK high is due to my approach to gaining control over the ADC (feel free to suggest a more direct foolproof way if you see one):
Here is a diagram first:
|----------------ONE CONVERSION CYCLE---------------------------|
ADC phase: |---------DRDY phase-----| |-------------DOUT phase--------|
DRDY/DOUT line state: HIGH [------------------VARIOUS--------------------] LOW
arduino action: |--delays doing nothing--| |-clocks out data-| |-wait for rising-edge interrupt-|
By holding SCK high for more than 4 ADC conversion cycles (but less than 20), I reset the ADC, as stated in the datasheet.
...Therefore, at the instant the reset is released (i.e., when I bring SCK back to LOW again), I know that I will be at a precise known time on the timing diagram of DOUT/DRDY line.
Then, for each ADC conversion cycle, I simply wait for the interrupt (Rising edge on DRDY/DOUT line) that guarantees that a new DRDY phase is starting (and thus a new conversion cycle, because each conversion cycle starts with a HIGH on the DRDY/DOUT line, and ends with a LOW, after DOUT finishes).
So, from the start of DRDY phase (also, start of conversion cycle), I delay for a time equal to the (datasheet-specified) period of the DRDY phase, at the end of which the DOUT phase begins.
At this point, I clock out the 3 bytes of data. After I'm done (I'll now be somewhere in the middle of DOUT phase, and thus the DRDY/DOUT is held LOW by the ADC), I again wait for a rising-edge interrupt for the next conversion cycle to begin, and so on.
The code I've written for this so far is not working (aaargh!) but I'm assume this is a good approach (it's based on my reading of a TI application note regarding the same ADC: http://focus.ti.com/lit/an/slaa242/slaa242.pdf