Correct, no pull-up or down resistors required on output pins. The pin will stay at the last commanded value.
When the ATMEGA chip resets it sets all I/O pins to input and engages all internal pull_up resistors.
And yes, the powerup or reset default for I/O pins is input mode, internal pull-ups disabled.
floresta, if you're so confident you're right why don't YOU go back to the spec sheet and point out where it says pull-ups are disabled at reset?
nowhere mentioned where the tri-state is also coupled with enabled pull-up or not at reset.
Just show me and could you stop blaming me twice or more for one mistake?
And now for some trivia. If I remember correctly the term 'tri-state' is specific to one manufacturer and the correct generic term is 'three-state' (I may have this backwards). This is not unlike the current situation with 'I2C' and 'TWI'.
Thank you floresta. I'm sorry for my attitude. After some searching, I realized tri-stated means the same as High-Z but still it's the property of the gate. The pull-up resistor seems to me to be "not a part of the tri-state gate". P77 is the diagram of a pin. I'll study it more.