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Topic: Logic not getting implemented (Read 166 times) previous topic - next topic

ishaanpuranik93


int DR=0;

void setup()

{
 
  Serial.begin(115200);

  pinMode(8, OUTPUT);
  pinmode(0, INPUT);
  pinmode(2, INPUT);
 
  // Enable single slope, 11-bit resolution PWM at 40kHz on 8 channels
  // PWM set-up on pins DAC1, A8, A9, A10, D9, D8, D7 and D6 for channels 0 through to 7 respectively
 
  REG_PMC_PCER1 |= PMC_PCER1_PID36;                                               // Enable PWM
  REG_PIOB_ABSR |= PIO_ABSR_P19 | PIO_ABSR_P18 | PIO_ABSR_P17 | PIO_ABSR_P16;     
  REG_PIOC_ABSR |= PIO_ABSR_P24 | PIO_ABSR_P23 | PIO_ABSR_P22 | PIO_ABSR_P21;     
  REG_PIOB_PDR |= PIO_PDR_P19 | PIO_PDR_P18 | PIO_PDR_P17 | PIO_PDR_P16;         
  REG_PIOC_PDR |= PIO_PDR_P24 | PIO_PDR_P23 | PIO_PDR_P22 | PIO_PDR_P21;         

  REG_PWM_CLK = PWM_CLK_PREA(0) | PWM_CLK_DIVA(1);  // Set the PWM clock A rate to 84MHz
 
  for (uint8_t i = 0; i < PWMCH_NUM_NUMBER; i++)        // Loop for each PWM channel (8 in total)
 
  {
    PWM->PWM_CH_NUM.PWM_CMR =  PWM_CMR_CPRE_CLKA;                 
    PWM->PWM_CH_NUM.PWM_CPRD = 840;  // Set the PWM period register 84MHz/(100kHz)=840;
  }
 
  REG_PWM_ENA = PWM_ENA_CHID7 | PWM_ENA_CHID6 | PWM_ENA_CHID5 | PWM_ENA_CHID4 |   
                PWM_ENA_CHID3 | PWM_ENA_CHID2 | PWM_ENA_CHID1 | PWM_ENA_CHID0;
 
}



void loop() {
 
 for (uint8_t i = 0; i < PWMCH_NUM_NUMBER; i++)                      // Loop for each PWM channel (8 in total)
  {
    if(analogRead(0)>analogRead(2))       
    {
      if(DR<255)
      {
        DR++;       
      }
      delay(10);
    }

    if(analogRead(0)<analogRead(2))
    {
      if(DR>0)
      {
        DR--;       
      }
      delay(20);
    }
    PWM->PWM_CH_NUM.PWM_CDTYUPD = DR;                           
  }
 
}

If I give constant duty ratio (PWM->PWM_CH_NUM.PWM_CDTYUPD = 400), without logic I get the required PWM output @100kHz.

But the moment I try to implement the above logic, the code does not work.

weird_dave

In what way does it not work? Is analogRead(0) ever greater than analogRead(2) to increase the value of DR above 0?

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