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Topic: SPI multi master (Read 9108 times) previous topic - next topic


Hello friends,

thanks for all the input!

I agree that the master/slave definition in this case is a little off, but usually the one who initiates the communication would be called the master which is why I chose the above labeling.

I did some tests with I2C but it wasn't fast enough for the application I had in mind.

missing a reading now and then will not be a problem as long as it doesn't happen too often.
Basically it is a low resolution large sensor array that will track objects and since I am aiming for high sampling rate an occasional lost or corrupt reading will be updated soon during the next cycle (or can even be corrected through interpolation on the software side).
So as long as it is the exception to miss a reading it won't matter.

[side note: I am aware that there seem to be a lot of different or "better" approaches like using cmos-sensors, cameras etc. but this design has been chosen for specific reasons and cannot be replaced]

Thank you very much for the schematics, it looks very interesting.

I think I will first try to reduce the total amount of modules in the system and then see if I can get this synchronization to work.

Thanks again for all the input, it is much appreciated! :)
Have a nice weekend!


I did some tests with I2C but it wasn't fast enough for the application I had in mind.

I was merely suggesting that I2C should be used to send a single byte (which would be fast) to notify the "central CPU" that the "peripheral" had data. After that you could use SPI for the actual transfer.
Please post technical questions on the forum, not by personal message. Thanks!

More info: http://www.gammon.com.au/electronics


low resolution large sensor array

Then if you can drop to 8-bits that will double the speed or more.

Rob Gray aka the GRAYnomad www.robgray.com


Jun 15, 2016, 07:19 am Last Edit: Jun 15, 2016, 07:22 am by Frédéric_Plante
I think your idea of the masters polling the SS line is good.
Use 2 pins to do it tho - one that is the SS output, have it drive an open collector driver that goes low out to the slave, and connect the open collector output to another input that you poll to see if it is free.
The open collector can just be a simple NPN transistor, drive the base high, pullup resistor for the high signal.  You will then drive SS high from the Arduino to start your transmission, and low to end, the slave will see that as the regular low & high.
Then you will not have to switch modes on the pin to see if the line is free. Either use a good fast transistor, or an IC equivalent such as 74LS06

As to how to keep more than one master from starting at the same time- can the masters talk to each other directly?
Then you could make a ring of comm's - 1 pulls SS low to start, and is connected to 2, pulling a line low to let 2 know it has started and stopped. 2 does the same to 3, which does the same to 4, etc, all way around until 10 gets back to 1 to start the process over. And maybe that line is just the pre-buffered SS line.  On power up, all would have to wait until 1 was ready to go to begin.
How far apart are the masters and slave?
I think the I2C network is totally meant to do that. I mean, using chips like PCF8574/PCF8575 to do multi chip select handling from multi SPI master to multi SPI slave. This way you can check from away if the SS/cs pin is in use and if not set/unset it.
As we fight our way northward into the great unknown, only that one thing remains certain...


Jun 09, 2017, 05:57 pm Last Edit: Jun 11, 2017, 01:34 am by jlsilicon
Why not share the (4) pins : CS, SCK, MOSI, MISO - using Resistors for high-impedence, and add a Single Shared-Reserve-Spi (SRS) pin.

1. Just check the CS if already Low - if Not and so Free, then :
2. bring down the (tied High) SRS pin, and check the CS again - if still Free then :
3. Release the SRS pin and bring down CS pin, check SRS pin - if still Free then :
4. bring down SRS pin again ,
5. - then use the SPI !

All this only needs (1) additional pin - the SRS - Shared-Reserve-Spi pin.

The idea is that a Master: alternates the RSV and CS pins - Reserving 1 pin while checking the other.
Any other Master will recognize 1 of the 2 pins Reserved, and so wait.

#ifdef  MC_1
  #define  DLY  5
#ifdef  MC_2
  #define  DLY  7
#ifdef  MC_3
  #define  DLY  9

int  Get_Spi_Bus()
 int Timeout = 1000;

 while( (Timeout --) > 0 )

   if(*RSV_P == H  &&  *CS_P == H)
     *RSV_P = L;
     if(*CS_P == H)
       *CS_P = L;
       *RSV_P = Z;
       if(*RSV_P == H)
         *RSV_P = L;

   delay_us(DLY * 4);


The Delay(DLY) is added to add variation of delay times between Micros,
to avoid Micros matching the Pin values in parallel (as unlikely as it is).
The different DLY values will guarantee to keep their Pin values out of sync.


Jun 11, 2017, 01:41 am Last Edit: Jun 12, 2017, 04:01 am by jlsilicon
This would allow multiple Masters on (1) SPI bus to share the Slave Devices.

A Star patter of Masters:

ARD1                 ARD2
Master               Master
       \            /
        +- IOExp   |
        +- /23s17  |
        +- /etc    |
       /            \
ARD3                 ARD4
Master               Master

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