I appreciate your feedback fat16lib, and you are doing some really interesting stuff.
But my original questions about the Chipstobits Storage Shield still remain unanswered. I am very interested in the shield but it seems the more I look through the documentation the more questions I have.
1)Can you reroute the SPI pins on the shield to the equivalent pins on the Mega in order to use hardware SPI with this shield and the Mega?
2)I downloaded the documentation and library and have been looking through it to try and answer some of these questions I have about the shield and I came across this:
#include <avr/pgmspace.h>
/*******************************************************************************//**
* \file spiMaster.cpp
* \author http://www.chipstobits.com - Steven Gifford
* \author Copyright 2009-2010 Chips To Bits
* \author Licensed under Creative Commons 3.0 Attribution, Share Alike
*
* Low level functions to support hardware level master SPI communications.
******************************************************************************/
#ifndef cbi
#define cbi(sfr, bit) (_SFR_BYTE(sfr) &= ~_BV(bit))
#endif
#ifndef sbi
#define sbi(sfr, bit) (_SFR_BYTE(sfr) |= _BV(bit))
#endif
// pin number on the port (not the chip)
#define MISO_PIN 4
#define MOSI_PIN 3
#define CLK_PIN 5
#define CS_PIN 2
// Data Direction port
#define MISO_PIN_PORT PORTB
#define MOSI_PIN_PORT PORTB
#define CLK_PIN_PORT PORTB
#define CS_PORT PORTB
// Data Direction Register
#define MISO_PIN_DDR DDRB
#define MOSI_PIN_DDR DDRB
#define CLK_PIN_DDR DDRB
#define CS_DDR DDRB
#define SELECT() cbi( CS_PORT, CS_PIN )
#define DESELECT() sbi( CS_PORT, CS_PIN )
On what board are the MISO, MOSI, and CLK on pins 3, 4, and 5? I know on the Uno they are 11-13 and on the Mega they are 50-52. What am I missing?
3)Does anyone have any idea how to get in contact with anyone at this website or under this Chipstobits organization?