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Topic: Arduino PCB question (Read 878 times) previous topic - next topic

LuisSoares

Hi,

I´m using 2 (fusing) of arduino designs to produce my own design, the arduino Mega and the Ethernet shield.

The question i have is related with the clearance of the central chips of each design, in this case ATMega2056 and Wiznet5100.

When i run de DRC in the PCB Layout it gives me a lot of clearance erros in the distance between pads, but when i lower the clearance distance this errors don´t disappear...

Does anyone has any idea why?

Best regards

a.d

It might be that the leads on the part are too fine a pitch for the PCB fab service you have selected, and there might be issues when making the boards.

Graynomad

Are the errors for the pads themselves or the solder resist?

Often with fine chips you have to define a solid block of resist over all the pins, otherwise the "sliver" between them is too fine.

______
Rob
Rob Gray aka the GRAYnomad www.robgray.com

MarkT

Eagle highlights the clearance overlaps for you - a screen grab of this might help work out what the issue is?
[ I won't respond to messages, use the forum please ]

CrossRoads

Which Design Rule Check are you using too?
Designing & building electrical circuits for over 25 years. Check out the ATMega1284P based Bobuino and other '328P & '1284P creations & offerings at  www.crossroadsfencing.com/BobuinoRev17.
Arduino for Teens available at Amazon.com.

LuisSoares


CrossRoads

Designing & building electrical circuits for over 25 years. Check out the ATMega1284P based Bobuino and other '328P & '1284P creations & offerings at  www.crossroadsfencing.com/BobuinoRev17.
Arduino for Teens available at Amazon.com.

LuisSoares

Copy paste of the conversation i had with the manufacturer:

Quote
1) If you run a DRC check on your board, you will see it has 371 errors. These are fairly serious. Several are due to insufficient clearance between pads of the Wiznet chip. We recommend:

a) You shrink the pads of the Wiznet chip by 0.5mil (0.01mm) on each side (0.02mm total) so that from pad-to-pad there is at least 6mil (0.16mm) spacing between the pads. Then, you can set the DRC clearance parameters to 6mil. That will make your board slightly cheaper to fabricate.

You can leave the Wiznet chip as it is but you will need to specify 5mil clearances when making the PCB, which will make it cost a bit more.

b) In the Net Classes (under the Edit menu) you have 6mil clearances and hole sizes set for different net classes. If you do not need these, set these to 0 else they interfere with the regular DRC.

c) Set the minimum drill diameter in the DRC to 15mil (0.381mm) for lowest cost. Looking at the density of your board it doesn't seem to need the 8mil drills you currently have specified.


.........

Quote
I just have one doubt, i have tried to lower the clearances to 3 mil for example, but still the errors don´t disappear, do you have any idea why this happens?
It is the net classes I mentioned in the last e-mail. Go to the Edit-->Net Classes menu. The settings there override the DRC.


And it worked :)

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