/* Analog 0-2 (PORTC) is hooked to a 3:8 line decoder (74LS138) which pull the Base of a PNP darlington (MPSA63) low through a 10k resistor for each row. +5V is connected to the Emitter of the PNP's, and all the anodes (+) of the leds for each row are connected to the Collector. Currently I'm trying to fix timing issues by putting some D-type positive edge triggered latches between PORTC and the 3:8 line decoder, clocked on the rising edge of XLAT, but this doesn't seem to help. I'm bringing the circuit in to the logic analyzer this weekend to see exactly when the ISR runs and how long it takes to shift in the GS data. Alex Leone, 2009-04-30*/
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