I tried to follow all the ideas generated by this thread and I've created an LTSpice simulation testbench. I would like to share with the Community the results, so I've created a github repository and I've placed the LTSpice source file on it. You can find the public github repository at this link: https://github.com/ethermania/FSKonDCbus
. Comments and contributions are welcomed!
Here is a brief explanation on what you can find on the file.
- A bus with parasitic capacitor (C4), resistor (R10) and a 50Hz 5V sine superimposed to simulate the effects of a possible noise on the line
- A MOSFet simulated Three state buffer injecting FSK on bus, with a protection resistor (R1). Note that the output stage generates a little short-circuit on the transitions. This is not important because this stage will be probably replaced.
- An Rx stage composed by a banbpass filter and the hypothetical comparator embedded on the Atmel processor
- A suitable power supply retrieving 5V from the bus, used to supply either the Tx than the Rx stages. A load resistor (R11) is added to simulate a realistic 0.5A consumption
- A set of 4 power supplies, with a 0.5A load, added to simulate other 4 nodes on the bus sinking (a lot) of current.
Running the simulation is the best option to understand what's happening on each stage. The most important thinks I can resume here are:
- At the Tx stage the current drawn by the bus is around 30mAmps. It's more than the maximum provided by the driver I've proposed on my previous post. Increasing the resistor R1 will limit the current but reduces the injected FSK voltage increasing the probability of a not well recovered at the Rx stage
- At the Rx stage is mandatory to have a band-pass filter in order to increase a little bit the noise immunity. Best would be to have two bandpasses centered at the FSK frequency (7.35kHz and 4.9kHz) each one, but this will increase the required components. I've added a simple 1st order active bandpass filter centered at 6kHz, with a gain of 12dB, with low cutoff frequency at 4kHz and high cutoff frequency at 8kHz. This increased (a lot) the overall Rx performances.
- The effect of a parasitic capacitors on the bus (I've set it at 1uF that's very huge.. I'm not expect to have something so big in the real world) is not dramatic. It decreases the overall FSK voltage at the Rx stage and increases the current sink from the Tx.
- The effect of a series resistor, introduced by the cable on the bus, is not interesting.
- The effect of a superimposed 50Hz (I've tested a superimposed value of 5V over the 24V of the bus. I think is very high compared on what we can find on the real world) is to change the duty cycle of the recovered signal. Not the frequency (as expected). When no data is present, a set of spurious transitions are generated by the comparator. They should be discarded by the soft-modem library (it's already performing like that).
- Coils characteristics are very important. I used a simulated real world coils I've found on the provided library and not a general coils.
- I've added a set of power supplies to simulate what's happening on the bus when more than one device is added. This power supplies are made by normal linear regulators so the current drawn from the bus is higher than what is expected.
- The current sink by the Rx stage is so low that's not important.
I've attached the schematics and the results of a simulation. In the simulation is present the decoded signal (green), the incoming signal from the bus (the blue, with a big 50Hz superimposed). The red line is the output of the bandpass filter (the signal will be feed on the Atmel pin).
Thank you for following me.