Im looking for some advice on reading analog audio data into an MKR ZERO (or similar SAM D21) board.
Currently I have an MKRZero board reading a WAV file from its onboard SD card. This works great with the ArduinoSound and I2S library amplitude analyser and FFT functions. I
I would now like to read audio data in via a 3.5mm jack (or similar) rather than the SD card. I have seen examples of a MEMS microphone breakout being used to send I2S data into a board (see https://www.arduino.cc/en/Tutorial/ArduinoSoundWhistleDetector) which looks very elegant.
However, I cant find any breakout board, hardware or information to stream/encode data in from an audio jack.
Does anyone have any experience or advice here?
Any advice would be much appreciated!!
Thanks for the reply!
I hadn't seen that, and it looks like a good option. I haven't ever used any Teensy hardware but I'll look into it.
It did seem strange to me that this wasn't a trivial thing for the MKRZero and Co. boards to do. I thought they were meant to be used for audio based projects!
You don't have to use Teensy hardware to use that board, you can use it with an MKRZero or any other board that has an I2S driver. I have been using I2S boards designed for the Raspberry Pi with my Arduinos, as well as that board.
Just an update, I've got my hands on a teensy audio board! I'm trying to set it up where the MKRZero is simply receiving I2S data from the teensy audio board (like in the whistle detect sketch I mentioned above).
I've read through the pinout documentation however I can figure out how I need to connect the two. The MKZero has I2S pins set up for WS, CLK and SD - word select, clock and data. Can you advise on the corresponding audio board pins? Should I expect the audio board to simply work as is, or will it need to be configured?
Thanks
EDIT: In the meantime I got a teensy3.2 set up and running with the teensy audio board. The teensy audio library looks pretty good too so maybe that is a solution
MCLK = master clock, usually a power of two times faster than the bit clock
BCLK = bit clock
LRCLK = left/right clock, basically the sample clock
And data in / out depending on whether DAC or ADC.
Nearly all chips require lock-step precision between the clocks - LRCLK must change on BCLK falling edge, BCLK and MCLK must be phase locked, and usually 64 BCLKs per LRCLK (though 48 or 32 are allowed too I think).
LRCLK frequencies are nominally 44.1kHz, 48kHz, 96kHz, 192kHz (commonest values)