what's it doing with the other 123 clock cycles (84MHz)?
The UDP write code isn't what It'd call "tight" (it calls SPI::transfer() N types instead of SPI::transfer(), for example (but I guess that's so it doesn't overwrite with "input")), but it doesn't look like it should be 123 clocks worth...
Udp.write(buf, size)
Socket::bufferData(... buf, size)
W5500Class::send_data_processing_offset(... buf, len)
W5500Class::write(... buf, len)
for (len)
SPI.transfer(buf[i])
byte SPIClass::transfer(byte _pin, uint8_t _data, SPITransferMode _mode) {
uint32_t ch = BOARD_PIN_TO_SPI_CHANNEL(_pin);
819d0: 290a cmp r1, #10
// SPI_CSR_DLYBCT(1) keeps CS enabled for 32 MCLK after a completed
// transfer. Some device needs that for working properly.
SPI_ConfigureNPCS(spi, ch, mode[ch] | SPI_CSR_SCBR(divider[ch]) | SPI_CSR_DLYBCT(1));
}
byte SPIClass::transfer(byte _pin, uint8_t _data, SPITransferMode _mode) {
819d2: b430 push {r4, r5}
uint32_t ch = BOARD_PIN_TO_SPI_CHANNEL(_pin);
819d4: d027 beq.n 81a26 <SPIClass::transfer(unsigned char, unsigned char, SPITransferMode)+0x56>
819d6: 2904 cmp r1, #4
819d8: d029 beq.n 81a2e <SPIClass::transfer(unsigned char, unsigned char, SPITransferMode)+0x5e>
819da: 2934 cmp r1, #52 ; 0x34
819dc: bf14 ite ne
819de: f44f 25e0 movne.w r5, #458752 ; 0x70000
819e2: f44f 2530 moveq.w r5, #720896 ; 0xb0000
819e6: bf14 ite ne
819e8: 2103 movne r1, #3
819ea: 2102 moveq r1, #2
// Reverse bit order
if (bitOrder[ch] == LSBFIRST)
819ec: 4401 add r1, r0
819ee: 7a0c ldrb r4, [r1, #8]
819f0: b91c cbnz r4, 819fa <SPIClass::transfer(unsigned char, unsigned char, SPITransferMode)+0x2a>
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
819f2: fa92 f2a2 rbit r2, r2
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV(uint32_t value)
{
uint32_t result;
__ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
819f6: ba12 rev r2, r2
_data = __REV(__RBIT(_data));
819f8: b2d2 uxtb r2, r2
uint32_t d = _data | SPI_PCS(ch);
if (_mode == SPI_LAST)
819fa: 2b01 cmp r3, #1
byte SPIClass::transfer(byte _pin, uint8_t _data, SPITransferMode _mode) {
uint32_t ch = BOARD_PIN_TO_SPI_CHANNEL(_pin);
// Reverse bit order
if (bitOrder[ch] == LSBFIRST)
_data = __REV(__RBIT(_data));
uint32_t d = _data | SPI_PCS(ch);
819fc: ea42 0205 orr.w r2, r2, r5
81a00: 6803 ldr r3, [r0, #0]
if (_mode == SPI_LAST)
d |= SPI_TDR_LASTXFER;
81a02: bf08 it eq
81a04: f042 7280 orreq.w r2, r2, #16777216 ; 0x1000000
// SPI_Write(spi, _channel, _data);
while ((spi->SPI_SR & SPI_SR_TDRE) == 0)
81a08: 6919 ldr r1, [r3, #16]
81a0a: 0789 lsls r1, r1, #30
81a0c: d5fc bpl.n 81a08 <SPIClass::transfer(unsigned char, unsigned char, SPITransferMode)+0x38>
;
spi->SPI_TDR = d;
81a0e: 60da str r2, [r3, #12]
// return SPI_Read(spi);
while ((spi->SPI_SR & SPI_SR_RDRF) == 0)
81a10: 691a ldr r2, [r3, #16]
81a12: 07d2 lsls r2, r2, #31
81a14: d5fc bpl.n 81a10 <SPIClass::transfer(unsigned char, unsigned char, SPITransferMode)+0x40>
;
d = spi->SPI_RDR;
81a16: 6898 ldr r0, [r3, #8]
// Reverse bit order
if (bitOrder[ch] == LSBFIRST)
81a18: b914 cbnz r4, 81a20 <SPIClass::transfer(unsigned char, unsigned char, SPITransferMode)+0x50>
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
81a1a: fa90 f0a0 rbit r0, r0
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV(uint32_t value)
{
uint32_t result;
__ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
81a1e: ba00 rev r0, r0
d = __REV(__RBIT(d));
return d & 0xFF;
}
81a20: b2c0 uxtb r0, r0
81a22: bc30 pop {r4, r5}
81a24: 4770 bx lr