In the /constraints/MKRVIDOR4000/vidor_s_pins.qsf file of the VidorFPGA project, the HDMI output pins are wrong:
set_location_assignment PIN_R16 -to oHDMI_TX[0]
set_location_assignment PIN_K15 -to oHDMI_TX[1]
set_location_assignment PIN_J15 -to oHDMI_TX[2]
set_location_assignment PIN_P16 -to oHDMI_TX[0](n)
set_location_assignment PIN_K16 -to oHDMI_TX[1](n)
set_location_assignment PIN_J16 -to oHDMI_TX[2](n)
set_location_assignment PIN_N15 -to oHDMI_CLK
set_location_assignment PIN_N16 -to oHDMI_CLK(n)
The correct pins are these:
[0]p = PIN_J15 >> BLU + SYNC
[0]n = PIN_J16
[1]p = PIN_K15 >> VERDE
[1]n = PIN_K16
[2]p = PIN_R16 >> ROSSO
[2]n = PIN_P16
Clkp = PIN_N15 >> CLOCK
Clkn = PIN_N16
Buses 0 and 2 are inverted. In addition to the error on the colors, bus 0 is used for synchronism, if you send the synchronisms on the bus 2 you do not see anything on the screen.
In fact in the file /ip/DVI_OUT/DVI_OUT.v the synchronisms are sent on all 3 buses, while it would be enough on bus 0, but the right one.