You're right, that was meant for @westfw.
So the FPGA implementation of the ZPU is essentially a 32bit CPU that interprets an 8bit instruction stream? Interesting. At 4 or more clocks per instruction, it's going to have a difficult time competing with even an AVR, except when the 32bit-ness improves things a great deal...
The problem I usually have with FPGA based CPUs is that their power-consumption really sucks compared to a dedicated microcontroller. The spartan 3e series needed here runs 75+ mA quiescent ?! (I couldn't figure out from the datasheet how much it would dissipate in "typical" operation; I guess that's too complicated for an FPGA. ("use XPower Estimator or XPower Analyzer that is part of the development environment.")