Everything works fine but realised I don't actually understand why 10k? is so convenient..
In the post I've linked, there is some debate on ADC timing and how the resistance value influences conversion speed. The Atmega2560 datasheet says:
The ADC is optimized for analog signals with an output impedance of approximately 10 k? or less. If such a source is used, the sampling time will be negligible. If a source with higher imped- ance is used, the sampling time will depend on how long time the source needs to charge the S/H capacitor, which can vary widely. The user is recommended to only use low impedant sources with slowly varying signals, since this minimizes the required charge transfer to the S/H capacitor.
As I arrange my pots in parallel, should I go for lower resistance values to decrease current or stick with 10k? pots (which seems to be a kind of holly grail)??
Hoping I can help you understand how the Atmega2560 ADC works. Essentially the ADC pin doesn't respond instantaneously to what it is sampling. On an ADC channel/pin of the Atmega2560 there is a capacitance that actually takes time to charge up to the voltage of the signal it is interfacing with. So there's actually a certain amount of time required for that capacitance to charge to get an accurate ADC reading. This is what the S/H (Sample and Hold) in the datasheet is referring to. How fast the capacitance on the ADC pin takes to charge depends on the output impedance (resistance) of the signal it's interfacing with. The lower the resistance, the higher the current that charges the ADC pin capacitance, the faster the ADC can sample. The datasheet recommends a maximum 10kOhm output impedance to interface with, so an ADC pin connected to the wiper of a 10k pot will result in the ADC pin never seeing more than 10kOhm. At one end of the pot it will see ~0 Ohms and at the other end of the pot it will see 10kOhms. As long as you use a pot less than 10k you'll be fine. And the lower the resistance of the pots you use, the faster the ADC sampling can sample without sacrificing accuracy.
And the lower the resistance of the pots you use, the faster the ADC sampling can sample without sacrificing accuracy.
Not quite, it is the shorter time it will take the S/H capacitor to charge. However, you don't get any faster sampling because it is all tied up with the system hardware and the internal switching of the multiplexer. You will see no speed increase if you drop this value. It is just that if you go over 10K the first sample you take when changing channels might not be quite right, especially if you have other pots on other analogue inputs.
Say you used 100K pots, and read them out one at a time, you would find that adjusting on pot affected the readings you got from all the others.
I was going off of my knowledge of ADC's in general. (It's been awhile since I took a look at the Atmega2560 datasheet.) In an ideal world where the ADC physical properties could be changed on the fly, a source lower resistance would allow for a faster ADC conversion would it not?
And using a lower than 10k source resistance would insure that the ADC capacitance had enough time to charge. I tend to stay away from the max's and min's I see in datasheets if possible on account of not getting burned with a part that doesn't quite meet the spec's.
And we haven't even started talking about Nyquist yet...
a source lower resistance would allow for a faster ADC conversion would it not?
Not a faster conversion that would remain the same. But it would make the sample and hold acquisition time slightly faster. However this is of minor significance compared to the time it takes to actually do the conversion.
Grumpy_Mike:
Say you used 100K pots, and read them out one at a time, you would find that adjusting on pot affected the readings you got from all the others.
Possibly, but I think the effect would be minimal, +/- 1 count at worst. The source resistance seen by a pin when fed from a 100k pot is 25k at worst (when the slider is mid position). Using a 47k pot would give a source resistance of 11.75k maximum, which is only just above the 10k recommendation. OTOH using 1M pots would certainly give noticeable interference between pins.
@antoine1, there are a few ways to use higher source resistance without the readings from different pins interfering with each other:
Do each analog read twice and throw away the first reading. Unfortunately this doubles the time taken to read from a pin (from about 110us to about 220us).
Patch the library to add a delayMicros call between switching the multplexer to the chosen pin and starting the conversion, right where there is already a commented out "delay(1);" statement. My measurements indicate that a delay of 10us is sufficient for source resistance up to 100k.
Add a capacitor from the pin to ground (47nF or 100nF should do the trick).
Add your own code to switch the multiplexer to the correct pin before you call analogRead, with a short delay between the two if necessary.
Possibly, but I think the effect would be minimal, +/- 1 count at worst.
There have been many posts from people saying the effect is much greater that this, in the range of the 20 to 30.
It is one of the 'standard' problems.
Agreed, it is one of the standard problems. When I did some tests on analogRead calls from 2 different pins at 0v and +5v through various resistors, I only saw that amount of interference with much larger source resistance, e.g. 1M.
