will a 1.8mm trace be able to handle 5 Amps
The theoretical min trace width for 5A is 1.38mm, so you should be ok but it also depends on the length of the run. That said it just seems a bit light on to me, but then I over-engineer everything. If you have room I would up the width.
Looking at the schematic, I assumed that opto had a logic output because of the way it was drawn, but I just looked at the datasheet and it actually has an open-collector output. I don't think it will effect you in this case but that's bad practice to show something that doesn't exist.
What values are the resistors on the outputs of the optos, I assume 350R because you have 351 next to them but in other places you use a different format, ie 10k. If they are really 350R where do you plan to get a 350R resistor? AFAIK the nearest you can get is 352R and that's an E192 value (ie very precise). Surely a 330R will do the same here.
I have to say that the schematic is still very badly drawn, and this
Is just mind-numbing. I'm collecting material for a "worst schematic practices I've seen" article and may include this. 
The PCB on the other hand seems quite well laid out at first glance. A couple of things though.
Clean this sort of thing up, it's a real mess and the sort of thing the auto-router would do, no human could run traces like that. If you are using the AR then clean up after it. BTW all ARs are crap, I don't know anybody that uses them.
Also right-angle corners are generally frowned upon because acute internal angles on a trace can form acid traps that eat out the trace a little more than the average. With a course board like this it won't matter but it's good to get into the habit of using 45-degree corner. But in some cases using 45-degree corners would reduce the trace length considerably, never a bad thing for high-current runs.
Some traces look very close
But that may just be an aliasing issue with the lo-res graphic. Have you set you design rules according to the fab house you will use and does the board pass DRC?
This is a bit odd, especially for what I assume is a high-current trace, why not pin through and go direct to the chip?
One way to spot this sort of dumb trace placement is to turn all layers off except the top copper. This removes the context of components and silk screen confusion and you can clearly see what the copper is doing. When you see something that looks a bit odd turn the other layers back on and see if it really has to be like that.
Then repeat with all other copper layers.
Rob