Hi pharaohamps,
It's also possible to change the frequency of generic clock (GCLK) that feeds the timers. There are 8 generic clocks: 0..3 are used by the Zero's core, but 4..7 are free.
This is done by setting the Generic Clock Generator Division register (GENDIV). GCLKs 3..8 allow an 8 bit divisor from 1 to 255.
So for example to feed a timer TC3 with a 16MHz clock from generic clock 4:
// Set up the generic clock (GCLK4) used to clock timers
REG_GCLK_GENDIV = GCLK_GENDIV_DIV(3) | // Divide the 48MHz clock source by divisor 3: 48MHz/3=16MHz
GCLK_GENDIV_ID(4); // Select Generic Clock (GCLK) 4
while (GCLK->STATUS.bit.SYNCBUSY); // Wait for synchronization
REG_GCLK_GENCTRL = GCLK_GENCTRL_IDC | // Set the duty cycle to 50/50 HIGH/LOW
GCLK_GENCTRL_GENEN | // Enable GCLK4
GCLK_GENCTRL_SRC_DFLL48M | // Set the 48MHz clock source
GCLK_GENCTRL_ID(4); // Select GCLK4
while (GCLK->STATUS.bit.SYNCBUSY); // Wait for synchronization
// Feed GCLK4 to TCC2 (and TC3)
REG_GCLK_CLKCTRL = GCLK_CLKCTRL_CLKEN | // Enable GCLK4 to TCC2 (and TC3)
GCLK_CLKCTRL_GEN_GCLK4 | // Select GCLK4
GCLK_CLKCTRL_ID_TCC2_TC3; // Feed GCLK4 to TCC2 (and TC3)
while (GCLK->STATUS.bit.SYNCBUSY); // Wait for synchronization
The timer's own prescaler (CTRLA register) can then be used to divide the frequency down further, for instance a prescaler divsor of 8 will set the timer at 2MHz.