I have a 1 Hz square wave connected to INT1, free-running so it is asynchronous WRT the µC. Using the following sketch, the interrupt appears to fire as soon as it's enabled; I consistently see 999 as the first number output. Then the time to the second interrupt varies, and is less than one second. I was expecting the opposite, i.e. the first number should be some random value less than one second, and then the rest should be one second apart.
I've been poring over the datasheet and I can't find anything that would indicate this behaviour, hoping someone can help. I've checked the interrupt flag (INTF1 in EIFR) to ensure it's not set going in, and it's not, have tried resetting it anyway, no joy, etc. etc.
I also tried using an Arduino to supply the 1 Hz signal, same results. Would have been surprised if that had made a difference, but it eliminates another possibility, if a remote one.
That did it! I had tried resetting the interrupt flag, and I had tried inhibiting interrupts, but I hadn't put them together. Investigating further, it sure looks like the act of enabling the INT1 interrupt causes the interrupt flag to be set. This code
Wow. That's strange. And annoying. I know some of the interrupt types are automatically cleared when enabled. I wonder if External Interrupts work differently by design, accident, or mistake.
Agree, not at all what I would have expected. Clearing on enable might make a little more sense. I wondered if it was some kind of latent thing, maybe while the bootloader did its thing or whatever, but it just doesn't make sense if the interrupt wasn't enabled along the way.
retrolefty:
Does changing the interrupt direction to raising edge give the same behaviour?
//external interrupt 1 on falling edge
Lefty
Yes, I tried that too. Just verified it again as well.
I found these two comments in an application note, but they don't fit the scenario here. It looks to me like enabling the interrupt causes the interrupt.
When changing the ISCn bit, an interrupt can occur. Therefore, it is
recommended to first disable INTn by clearing its Interrupt Enable bit in the
EIMSK Register.
Before enabling an interrupt, it is recommended to clear the flag bit of the
corresponding interrupt because when the flag bit is set, the interrupt will be
triggered the moment we enable the interrupt.
AHA! That app note was right. Setting the sense control bit (ISCxx) causes the interrupt. Using the code below, I didn't see it earlier, but by adding delay(1) I see it now. Wasn't seeing it before no doubt because the code was picking up EIFR before the four clock cycles it takes to respond to an interrupt.
So the cli() and sei() can be dispensed with, and the minimal code to do the job ends up like this, assuming the interrupt is disabled going in:
EICRA = _BV(ISC11); //external interrupt 1 on falling edge
_delay_loop_1(2); //allow time for the interrupt caused by setting ISCxx (#include <util/delay_basic.h>)
EIFR = _BV(INTF1); //clear the interrupt flag
EIMSK = _BV(INT1); //enable external interrupt 1
Edit 26Jan2013: Playing with this again today, it looks like the call to _delay_loop_1() is not needed. Might have gotten myself wrapped around the axle a bit there last night
Knowing what I know now, it seems it would have to be one of the latter. Maybe someone can think of a reason that it should work this way, but at the moment, I am at a loss
Maybe someone can think of a reason that it should work this way
From a HW point of view, I can imagine circuitry that detects falling and rising edges, as well as levels, that would be active all the time (whether or not interrupts are enabled.) Enabling the pin change interrupt causes an immediate interrupt, because sure enough there HAS BEEN a falling edge some time in the past, even though it wasn't set up to cause interrupts. I think the timer interrupts work like this too. If you've been running the timer for a while without paying attention to the pieces that cause interrupts, the "overflow" bit will be set (you never cleared it, after all) and will cause an interrupt as soon as you enable timer overflow interrupts.
Maybe someone can think of a reason that it should work this way
From a HW point of view, I can imagine circuitry that detects falling and rising edges, as well as levels, that would be active all the time (whether or not interrupts are enabled.) Enabling the pin change interrupt causes an immediate interrupt, because sure enough there HAS BEEN a falling edge some time in the past, even though it wasn't set up to cause interrupts. I think the timer interrupts work like this too. If you've been running the timer for a while without paying attention to the pieces that cause interrupts, the "overflow" bit will be set (you never cleared it, after all) and will cause an interrupt as soon as you enable timer overflow interrupts.
Good point. And indeed as one example the datasheet has a similar warning that changing the settings for the analog comparator can cause an interrupt. Unless I missed it though, they must have forgotten to mention this one in connection with external interrupts.
I did google around and also searched the forum a bit to see if anyone had noticed this before, and didn't come up with anything. On the one hand that's hard to believe, but being a sort of boundary condition thing, people might just tend to code around it if it makes a difference to them rather than digging into it.
As I also discovered (code in #9 above), the Arduino interrupt functions also cause this spurious interrupt. Do you guys think it's worth raising an issue on? Seems pretty serious to me, I don't expect a freebie interrupt just because I enable them. Simple enough fix, but I was looking at WInterrupts.c and I see it would have to be made in a couple dozen places!