Awesome work so far Rob.
What a confusing data sheet.
Looks like there are multiple sets of SPI controllers - I don't see how they make it to IO pins tho.
For example PA25-26-27-28 make up SPI 0 with 3 additional chip selects on PA29-30-31 - where are are PA30-31 on the Due schematic? PA25-26-27 only seem to be on a 2x3 header?
Similarly for PE28-29-30-31 for 2nd SPI - what pins do they get multiplexed onto? I can't tell from the data sheet, same for the additional chip selects on PF0,1,2.