I found the problem! (some hours later... ) Now the code is working!
When I changed pins so they corresponded to the ItsyBitsy M0 layout (PAXX to Digital pin) and the M0 data sheet and the E or F column in the Table 6-1. PORT Function Multiplexing in the ATMEL SAMD21G
data sheet. Previous pairs (11,13 ) and (10,12) of pins had the same (W O numbers)
TCC0 (W O 0) E PA08 = 4
TCC0 (W O 1) E PA09 = 3
TCC0 (W O 2) F PA18 = 10
TCC0 (W O 3) F PA19 = 12
CODE:
// Output 20kHz PWM on timer TCC0 (8-bit resolution)
void setup()
{
REG_GCLK_GENDIV = GCLK_GENDIV_DIV(3) | // Divide the 48MHz clock source by divisor 3: 48MHz/3=16MHz
GCLK_GENDIV_ID(4); // Select Generic Clock (GCLK) 4
while (GCLK->STATUS.bit.SYNCBUSY); // Wait for synchronization
REG_GCLK_GENCTRL = GCLK_GENCTRL_IDC | // Set the duty cycle to 50/50 HIGH/LOW
GCLK_GENCTRL_GENEN | // Enable GCLK4
GCLK_GENCTRL_SRC_DFLL48M | // Set the 48MHz clock source
GCLK_GENCTRL_ID(4); // Select GCLK4
while (GCLK->STATUS.bit.SYNCBUSY); // Wait for synchronization
// Enable the port multiplexer for the 4 PWM channels: timer TCC0 outputs
const uint8_t CHANNELS = 4;
const uint8_t pwmPins[] = { 4, 3, 10, 12 }; // TCC0 (W O 0) E PA08 = 4, TCC0 (W O 1) E PA09 = 3, TCC0 (W O 2) F PA18 = 10, TCC0 (W O 3) F PA19 = 12
for (uint8_t i = 0; i < CHANNELS; i++)
{
PORT->Group[g_APinDescription[pwmPins].ulPort].PINCFG[g_APinDescription[pwmPins*].ulPin].bit.PMUXEN = 1;
_ }_
_ // Connect the TCC0 timer to the port outputs - port pins are paired odd PMUO and even PMUXE*_
* // F & E specify the timers: TCC0, TCC1 and TCC2*
* PORT->Group[g_APinDescription[4].ulPort].PMUX[g_APinDescription[4].ulPin >> 1].reg = PORT_PMUX_PMUXO_E | PORT_PMUX_PMUXE_E;
PORT->Group[g_APinDescription[10].ulPort].PMUX[g_APinDescription[10].ulPin >> 1].reg = PORT_PMUX_PMUXO_F | PORT_PMUX_PMUXE_F;*
* // Feed GCLK4 to TCC0 and TCC1*
* REG_GCLK_CLKCTRL = GCLK_CLKCTRL_CLKEN | // Enable GCLK4 to TCC0 and TCC1*
* GCLK_CLKCTRL_GEN_GCLK4 | // Select GCLK4*
* GCLK_CLKCTRL_ID_TCC0_TCC1; // Feed GCLK4 to TCC0 and TCC1*
* while (GCLK->STATUS.bit.SYNCBUSY); // Wait for synchronization*
* // Dual slope PWM operation: timers countinuously count up to PER register value then down 0*
* REG_TCC0_WAVE |= TCC_WAVE_POL(0xF) | // Reverse the output polarity on all TCC0 outputs*
* TCC_WAVE_WAVEGEN_DSBOTTOM; // Setup dual slope PWM on TCC0*
* while (TCC0->SYNCBUSY.bit.WAVE); // Wait for synchronization*
* // Each timer counts up to a maximum or TOP value set by the PER register,*
* // this determines the frequency of the PWM operation:*
* // 400 = 20kHz*
* REG_TCC0_PER = 400; // Set the frequency of the PWM on TCC0 to 20kHz*
* while(TCC0->SYNCBUSY.bit.PER);*
* // The CCBx register value corresponds to the pulsewidth in microseconds (us)*
* REG_TCC0_CCB0 = 0; // TCC0 CCB0 - 200 = 50% duty cycle on D2 (0-400)
_ while(TCC0->SYNCBUSY.bit.CCB0);_
REG_TCC0_CCB1 = 0; // TCC0 CCB1 - 200 = 50% duty cycle on D2 (0-400)
_ while(TCC0->SYNCBUSY.bit.CCB1);_
REG_TCC0_CCB2 = 0; // TCC0 CCB2 - 200 = 50% duty cycle on D2 (0-400)
_ while(TCC0->SYNCBUSY.bit.CCB2);_
REG_TCC0_CCB3 = 0; // TCC0 CCB3 - 200 = 50% duty cycle on D2 (0-400)
_ while(TCC0->SYNCBUSY.bit.CCB3);_
_ // Divide the 16MHz signal by 1 giving 16MHz (62.5ns) TCC0 timer tick and enable the outputs*_
* REG_TCC0_CTRLA |= TCC_CTRLA_PRESCALER_DIV1 | // Divide GCLK4 by 1*
* TCC_CTRLA_ENABLE; // Enable the TCC0 output*
* while (TCC0->SYNCBUSY.bit.ENABLE); // Wait for synchronization*