This question is directed at philippe_at_sysemb's FPGABlinkLED_Sketch -
1st - philippe_at_sysemb - thanks for posting that - good job - I've got that running with an LED attached to '6' - but I have a question:
I've tried to merge with another sketch (thought I saw a thread about this somewhere) and now it doesn't run - I've tried commenting out a few things but it ends up with the FPGA apparently not running - and I'm not even sure my merged sketch is doing anything useful by that point.
Since I imagine some others have merged this into an existing sketch - can someone post do's and don'ts for this so the rest of us can know the rules for merging this into existing code?
my tutorials aim to show FPGA beginners how they can reprogram the card's FPGA for their own needs.
ARDUINO's sketches specific to the MKR VIDOR 4000 use a configuration that must be compile using the method described in [WORKFLOW RELEASE] post.
I plan to present in following weeks (I am very busy at the moment) a FPGA configuration that will include most of the features available on ARDUINO's current configuration, but without INTEL proprietary IP, bus or softcore.
I think Wishbone and OpenMSP430 would be a good choice.
I think merging sketch will work only if they use same FPGA image or you have to build FPGA image that have all required IP blocks and use generated libraries from there.
philippe_at_sysemb:
I plan to present in following weeks (I am very busy at the moment) a FPGA configuration that will include most of the features available on ARDUINO's current configuration, but without INTEL proprietary IP, bus or softcore.
I think Wishbone and OpenMSP430 would be a good choice.
I recommend to check LatticeMico32 or soc-lm32 project. That was already ported to Xilinx Spartan6 (Milkymist soc) and Altera Cyclone IV (DE1 eval board from terasic). This may provide littlebit better performance.
I was planning to use direct JTAG to avalon_mm. In most cases NIOS is only writing data from mailbox to IP so why not use direct access. Maybe need some FIFO/Buffer there but it should be OK. Only GFX acceleration need softcore there or just create "state machine" for that.
Edit:
It seems that soc-lm32 project is currently "dead" last update from 2010
I appreciate the answer. We're all busy - no rush - just wanted to ask.
I believe all that is needed to make this work is just to control the JTAG pins at the proper time during code loading - I thought maybe someone had worked that out already - but I will take a look at that. I am assuming right now that is possible with the 'sketch' approach.
I have sketches that run code only on the SAM and NINA - loading the Cyclone 10 LP while controlling the necessary pins - probably JTAG and maybe a few more; will allow the code to be loaded.
I am not necessarily asking how to make the FPGA code "workflow" work with what you've done - I'd rather have
a sketch that's independent so to speak of the "workflow" that just interfaces via controlled pins; like how the JTAG pins will be controlled to make this work. I thought this had been worked out already.
FPGA image (app.tff) is uploaded when you upload sketch. It's placed outside of SAMD21 flash area so bootloader knows to start write it to FPGA configuration flash. So you can't update it in runtime from SAMD21 flash.
You can use USB Blaster clone sketch for updating FPGA image in runtime but you needed to be connected to PC with Quartus. Also when developing FPGA image for internal logic analyzer you need USB Blaster library in sketch. There are some limitation. Like loop execution time. Long loop will cause BSOD for windows.
Lets hope that they will get cloud environment up and running. This should simplify FPGA image creation for arduino. What I understand that you just select used ip+libraries and this will check if it fits and then create image for FPGA. After that you just create sketch that uses it and clousd will compile it to single image.
