FPGA Block Wishlist

hi guys,
thanks for the input. the resources and capabilities ew have on Vidor are a bit limited for serious vision applications so don't expect to do on it openCV stuff, not at least the fanciest things at least.
one of the main limitations is memory bandwidth (to keep costs low we just have a SDRAM) so we can go very fast if we can process on line but not so much if we have to store frames in memory.
you will notice that the VidorGraphics image actually only uses 16 bits per pixel for this reason even if image from camera can be up to 30 bits per pixel.
just to do some math, we have 100 MHz/16 bit bandwidth on SDRAM; if we consider a pixel made of 16 bits then we have 100 MPixel/sec gross bandwidth. VGA output requires 64048060 =about 18.5 MPixel/Sec. if we need to write it, read it back and also read back another layer for the OSD we already consumed more than half the bandwidth, then we need to consider some bandwidth to write OSD and some extra bandwidth for access overhead (typically up to 20%) so you can easily see where i'm going.

in any case operations such as edge detection (we do that in QR finder), filtering, and eventually also downscaling can be done pretty much on the fly and if we don't need to have OSD (or we want to have a lower resolution one) then we can easily go for 24 bits per pixel all the way.

in any case please try to be a bit more specific on the cores you would like to see and most importantly for which application so that we can try to put our effort where more people see value.