I'm using the following code to synchronize three channels and output a pair of complementary outputs per channel.
void setup() {
PMC->PMC_PCER1 |= PMC_PCER1_PID36; //Enable PWM (Power On)
PWM->PWM_DIS = PWM_DIS_CHID0; //Disable PWM on Channel 0
//PWM->PWM_DIS = PWM_DIS_CHID1;
PIOC->PIO_PDR |= PIO_PDR_P3 | PIO_PDR_P5 | PIO_PDR_P7; // Setting pins 3,5,7 (DUE Pins 35, 37, 39) to PWM Peripheral, not GPIO
PIOC->PIO_ABSR |= PIO_PC3B_PWMH0 | PIO_PC5B_PWMH1 | PIO_PC7B_PWMH2; // Setting pins to Peripheral B
PIOC->PIO_PDR |= PIO_PDR_P2 | PIO_PDR_P4 | PIO_PDR_P6; // Setting pins 2,4,6 (DUE Pins 34, 36, 38) to PWM Peripheral, not GPIO
PIOC->PIO_ABSR |= PIO_PC2B_PWML0 | PIO_PC4B_PWML1 | PIO_PC6B_PWML2; // Setting pins to Peripheral B
PWM->PWM_CLK = PWM_CLK_PREA(0) | PWM_CLK_DIVA(42); //Set PWM clock rate to 2MHz (84MHz/42)
PWM->PWM_CH_NUM[0].PWM_CMR = PWM_CMR_CPRE_CLKA; // Period is left aligned,clock source is CLKA on Channel 0
REG_PWM_SCM |= PWM_SCM_SYNC0 | PWM_SCM_SYNC1 | PWM_SCM_SYNC2; // Synchronizing of Channels 0, 1 and 2
//PWM->PWM_CLK = PWM_CLK_PREA(1) | PWM_CLK_DIVA(42);
//PWM->PWM_CH_NUM[1].PWM_CMR = PWM_CMR_CPRE_CLKA;
REG_PWM_CPRD0 = 1000000; //Channel 0 Period f = 2MHz/(2*CPRD)
REG_PWM_CDTY0 = 200000; //Channel 0 Duty Cycle x% = (CDTY/ CPRD)*100%
REG_PWM_CPRD1 = 1000000;
REG_PWM_CDTY1 = 1000000;
REG_PWM_CPRD2 = 1000000;
REG_PWM_CDTY2 = 0;
PWM->PWM_ENA = PWM_ENA_CHID0; // Enable PWM on Channel 0
//PWM->PWM_ENA = PWM_ENA_CHID1;
//NVIC_EnableIRQ(TC0_IRQn); // enable TC0 interrupts
}
void loop() {
// put your main code here, to run repeatedly:
}
When the duty cycle is set to 0%, 20%, 40%, 60%, 80% and 100% (0, 200000, 400000, 600000, 800000, 1000000) it outputs correctly. However any other value just gives me the output for 100% duty cycle. Can anyone explain this to me and offer some guidance on how to rectify this problem?