ATTiny85 tone() core?

By default, for the ATtiny85 processor, timer 1 is used for millis. Timer 0 is used for everything else (tone). That can be reversed with a compile-time switch.

Open the datasheet...

Navigate to the 1. Pin Configurations section. Pins marked with OC (oh-see) are Output Compare (PWM) pins. The number after OC is the timer. The letter after is the channel.

Find all pins marked with OC0 (oh-see-zero): PB1 and PB0. PB1 and PB0 are potentially "tone output pins".

The problem with PB1 (OC0B) is that it overlaps with an output from the other timer (OC1A). Which output is used is determined by another compile-time switch. By default, "phase correct PWM" is favored so OC0B is used.

So, by default, PB1 and PB0 are the "tone output pins".