chriskner:
Do not connect two Due's together on a common I2C bus without a buffer of some sort. The combination of both boards, and their pull-up resistors in parallel, will unnecessarily stress the DUE's TWI pins. I recommend that the on-board pull-ups be removed from the DUE's pcb by default. Use larger external pull-up resistors.
How big? Check this out:
http://www.edn.com/design/analog/4371297/Design-calculations-for-robust-I2C-communications
Hi Chris,
Great link! Someone pointed me to this post recently in concern about the 1.5K pullups I'd used in a Due-compatible design (the Freetronics EtherDue). The 1.5K values I'd used were the same as the Due reference design. I calculate that under normal circumstances (including connecting two Dues together over i2c) the onboard pullup selection is fine, no need to remove them.
According to the SAM3X8E datasheet Table 46-2, the TWI pins on the Due (ports PB12,13 & PA17,18) can individually sink 6mA for VOL = 0.4V, or sink 9mA in "Relaxed" mode for VOL=0.6V.
Pulling 3.3V down to 0.4V through a 1.5K resistor means sinking 1.93mA. So you can connect three Dues to the same i2c bus, if you needed to, for a combined super low 500 ohm pullup resistance, before you risk the low level voltage floating above 0.4V.
If you're feeling adventurous you could add a fourth and probably a fifth Due to a common i2c bus and push the low voltage up to 0.6V ("relaxed mode") before you risk damaging anything by sinking more than 9mA (the Dues will still be able to talk to each other, as their VIL is maximum 1V.)
It is definitely worth checking any other i2c device's specifications though, to make sure they can sink at least 2mA at 0.4V. This should be well within the limit for most devices, though. Mixing more than one Due on a single i2c bus with multiple other devices also on the bus is perhaps potentially risky, as by this point you have relatively high currents (4mA, 6mA) which may exceed some device limits. The only way to be sure would be to check each device's datasheet.
Why are the comparatively low resistance values on the Due design useful, when most i2c pullups are 4.7k or 10k? The reason is probably to deal with situations of high bus capacitance, especially when using fast mode (400kHz.) This is discussed in the excellent PDF you linked above. At 400kHz it's probably not as essential as it would be if the Due supported 1Mbit or 3.4Mbit "Faster" TWI, but it's still helpful to have the bus return to a "high" value as quickly as possible.
TLDR: Unless I missed something (and please tell me if I did), I wouldn't worry about removing the Due's standard pullups under normal conditions.