In the comments we find // The GPIO pins controlled by the FPGA start from 100 // Ok, so we know now that the FPGA contains the extended GPIO IP // The GPIO pins controlled by the FPGA start from 100 // Please refer to the online documentation for the actual pin assignment So why is the code…

Question About VidorTestSketch

sandeepmistry August 7, 2018, 1:43pm 2

These comments are incorrect, I've opened an issue on our internal issue tracker to address them, once we have an update we'll write here.

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