aster94:
better to wait, meanwhile you could see the schematics here and you should start to find the resisors for the voltage divider to check the k-line (12-14V) with the logic analyzer (max 5V) some value like 10k and 5k would works well
I used 10k and 20k - the curiosity just got the better of me and I hooked up the logic analyzer to the bike.
I've attatched the whole analyzer file to the post (used Pulseview), but here is an overview of the interesting parts.
D0 is TX
D1 is RX
D2 is KLine with voltage divider. high was around 4.2 volts.
Pulling K-Line low works well (echo on RX).
Pulling K-Line high after ~70ms
After waiting ~120ms, the sending happens. I think this is where everything is somehow effed:
For some reason, it doesn't get to send the second FF. It should be sending "FE 04 FF FF", but the second FF gets cut off? It also echos F8 FF back right away for some reason. The K-Link also stays low for a long time during sending the 04, and looks like it doesn't react to the sent signals?
Here, it should be sending "72 05 00 F0 99" but it looks like it's sending "78" as the first byte. Maybe the serial isn't ready yet? At other points in time I also got things like "72 02 00 F0 99" and other strange responses.
I assume this confirms that we just need to wait for the SOIC to DIP adapter and that's fine, just wanted to share because I feel this confirms something wrong with my setup.
odb1.zip (960 Bytes)